Structured Latch and Local-Clock-Buffer Planning

Abstract

Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

1 . A method, comprising:
 extracting a datapath graph from a logic representation of a datapath, wherein said datapath graph comprises latches, pins, and their logical connections;   prior to physically laying out said datapath, assigning locations for said latches based upon said a datapath graph in such manner as to optimize said datapath according to a predetermined criteria; and   wherein said method is characterized as being a physical synthesis of an integrated circuit, and wherein at least said assigning step is executed using a computer.   
     
     
         2 . The method of  claim 1 , wherein said method further comprises:
 dividing said latches into banks based upon a logic nature of said latches; and   in said assigning step, grouping together same bank latches in a y-direction, wherein said y-direction is parallel with the direction of said datapath.   
     
     
         3 . The method of  claim 2 , wherein said method further comprises:
 using attractors between said same bank latches in order to force said grouping in said y-direction.   
     
     
         4 . The method of  claim 2 , wherein said method further comprises:
 in said assigning step, placing said same bank latches in an x-direction, using min-cost network flow algorithmic or linear programming approaches, wherein said x-direction is perpendicular to said y-direction.   
     
     
         5 . The method of  claim 4 , wherein said method further comprises:
 in said placing of said same bank latches, locating free spots lined up in said x-direction and calculate a placement cost for said free spots based on misalignments in said y-direction; and   inserting said same bank latches in optimal free spots having minimum of said placement cost.   
     
     
         6 . The method of  claim 5 , wherein said method further comprises:
 successively continue until all said same bank latches have been placed.   
     
     
         7 . The method of  claim 4 , wherein said method further comprises:
 ensuing said placing of said same bank latches, placing local clock buffers (LCBs) based on minimizing a capacitive load on said LCBs, wherein said LCBs are configured to drive said latches.   
     
     
         8 . The method of  claim 4 , wherein said method further comprises:
 ensuing said placing of said same bank latches, placing local clock buffers (LCBs) based on limiting the maximum number of said same bank latches per each of said LCBs, wherein said LCBs are configured to drive said latches.   
     
     
         9 . The method of  claim 1 , wherein said method further comprises:
 deriving said predetermined criteria from functions related to minimizing total wire length in said datapath, or related to minimizing wire length perpendicular to the direction of said datapath, or related to minimizing a combination of total wire length of said datapath and of wire length perpendicular to the direction of said datapath.