Sram with buffered-read bit cells and its testing

Abstract

An SRAM with buffered-read bit cells is disclosed (FIGS. 1 - 6 ). The integrated circuit includes a plurality of memory cells ( 102 ). Each memory cell has a plurality of transistors ( 200, 202 ). A first memory cell (FIG. 2 ) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit ( 104 ) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7 - 10 ).

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a functional memory having a plurality of memory cells arranged in rows and columns and operable through row and column peripheral circuitry for write and read operations, each memory cell having a plurality of transistors;   a first memory cell of the plurality of memory cells arranged to store a data signal in response to an active write word line and to produce the data signal in response to an active read word line; and   a test circuit formed on the integrated circuit operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell.   
     
     
         2 . An integrated circuit as in  claim 1 , wherein the integrated circuit receives data signals at a data input (Din) terminal in a functional mode and produces data signals at the data input terminal in a test mode. 
     
     
         3 . An integrated circuit as in  claim 1 , wherein the first memory cell is an eight transistor (8T) static random access memory (SRAM) cell. 
     
     
         4 . An integrated circuit as in  claim 1 , operable to activate the write word line and the read word line at a first time in a test mode. 
     
     
         5 . An integrated circuit as in  claim 1 , wherein the current and voltage characteristics determine a threshold voltage of said each transistor of the plurality of transistors of the first memory cell. 
     
     
         6 . An integrated circuit as in  claim 1 , wherein the current and voltage characteristics determine a leakage current of said each transistor of the plurality of transistors of the first memory cell. 
     
     
         7 . An integrated circuit as in  claim 1 , wherein said each transistor of the plurality of transistors of the first memory cell has a current path, and wherein the test circuit is operable to test current and voltage characteristics of at least one transistor of the plurality of transistors of the first memory cell for any direction of current flow in the current path. 
     
     
         8 . An integrated circuit as in  claim 1 , wherein the test circuit is operable to apply a first range of voltages to a first terminal of at least one transistor of the plurality of transistors of the first memory cell and to apply a second range of voltages to a second terminal of the at least one transistor to test current and voltage characteristics of said at least one transistor. 
     
     
         9 . An integrated circuit, comprising:
 a functional memory having an array of memory cells arranged in rows and columns and operable through row and column peripheral circuitry for write and read operations, each memory cell having a latch portion and a buffer portion;   a first memory cell of the plurality of memory cells arranged to store a data signal in the latch portion in response to a write signal; and   a selection circuit coupled to receive a mode control signal,   wherein the selection circuit is arranged to receive the data signal from the buffer portion of the first memory cell in response to a first state of the mode control signal, and   wherein the selection circuit is arranged to receive the data signal from the latch portion of the first memory cell apart from the buffer portion in response to a second state of the mode control signal.   
     
     
         10 . An integrated circuit as in  claim 9 , wherein the selection circuit is arranged to receive the data signal in a functional mode. 
     
     
         11 . An integrated circuit as in  claim 9 , wherein the selection circuit is arranged to receive the data signal in a test mode. 
     
     
         12 . An integrated circuit as in  claim 9 , wherein the first memory cell is a static random access memory (SRAM) cell. 
     
     
         13 . An integrated circuit as in  claim 9 , comprising a test circuit operable to test current and voltage characteristics of a plurality of transistors of the first memory cell. 
     
     
         14 . An integrated circuit as in  claim 13 , wherein the current and voltage characteristics determine a threshold voltage of each transistor of the plurality of transistors. 
     
     
         15 . An integrated circuit as in  claim 13 , wherein the current and voltage characteristics determine a leakage current of each transistor of the plurality of transistors. 
     
     
         16 . A method of operating a functional memory having a plurality of memory cells arranged in rows and columns and having functional and test modes, comprising the steps of:
 activating a write word line of a row of memory cells through row peripheral circuitry in the functional mode;   storing a data signal in a memory cell of the functional memory in response to activating the write word line;   activating a read word line in the functional mode through the row peripheral circuitry;   producing the data signal from the memory cell of the functional memory in response to activating the read word line;   operating the functional memory in the test mode; and   testing current and voltage characteristics of each transistor of a plurality of transistors of the memory cell in response to operating the functional memory in the test mode.   
     
     
         17 . A method as in  claim 16 , wherein the memory cell is an eight transistor (8T) static random access memory (SRAM) cell. 
     
     
         18 . A method as in  claim 16 , comprising the steps of:
 activating the write word line at a first time in the test mode; and   activating the read word line at the first time in the test mode.   
     
     
         19 . A method as in  claim 16 , comprising the step of determining a threshold voltage of said each transistor of a plurality of transistors of the memory cell in response to the step of testing current and voltage characteristics. 
     
     
         20 . A method as in  claim 16 , comprising the step of determining a leakage current of said each transistor of a plurality of transistors of the memory cell in response to the step of testing current and voltage characteristics.