Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages

Abstract

A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

What is claimed is: 
     
         1 . A chip package comprising:
 a chip carrier;   a chip disposed over and electrically connected to a chip carrier top side;   an electrically insulating material disposed over and at least partially surrounding the chip;   one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip;   a further electrically insulating material disposed over a chip carrier bottom side;   wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.   
     
     
         2 . The chip package according to  claim 1 ,
 wherein the chip carrier comprises a lead frame carrier.   
     
     
         3 . The chip package according to  claim 1 ,
 wherein the chip carrier comprises an electrically conductive material, the electrically conductive material comprising at least one from the following group of materials, the group of materials consisting of: copper, nickel, iron, silver, gold, palladium, phosphorous, copper alloy, nickel alloy, iron alloy, silver alloy, gold alloy, palladium alloy, phosphorous alloy.   
     
     
         4 . The chip package according to  claim 1 ,
 wherein the chip is configured to carry a voltage ranging from about 5 V to about 1200 V.   
     
     
         5 . The chip package according to  claim 4 ,
 wherein the chip comprises at least one device from the following group of devices, the group consisting of: a transistor, a power transistor, a power MOS transistor, a power bipolar transistor, a power field effect transistor, a power insulated gate bipolar transistor, a thyristor, a MOS controlled thyristors, a silicon controlled rectifier, a power schottky diode, a silicon carbide diode, a gallium nitride device, a multi-chip device.   
     
     
         6 . The chip package according to  claim 1 ,
 wherein the chip is electrically connected to the chip carrier via at least one contact pad formed over a chip bottom side.   
     
     
         7 . The chip package according to  claim 1 ,
 wherein the chip is electrically connected to the chip carrier via an electrically conductive medium, the electrically conductive medium comprising at least one from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, an electrically conductive paste, a nanopaste, an adhesive, an electrically conductive adhesive.   
     
     
         8 . The chip package according to  claim 1 ,
 wherein the electrically insulating material comprises at least one from the following group of materials, the group consisting of: filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, a thermoplastic material, filler particles, fiber-reinforced laminate, fiber-reinforced polymer laminate, fiber-reinforced polymer laminate with filler particles.   
     
     
         9 . The chip package according to  claim 1 , further comprising
 one or more electrical interconnects formed through the electrically insulating material;   wherein the one or more electrical interconnects are configured to electrically connect one or more contact pads formed over a chip top side to the one or more electrically conductive contact regions.   
     
     
         10 . The chip package according to  claim 1 , further comprising
 one or more joining structures electrically connected to the one or more electrically conductive contact regions.   
     
     
         11 . The chip package according to  claim 10 ,
 wherein the one or more joining structures comprises at least one from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, an electrically conductive paste, a nanopaste.   
     
     
         12 . The chip package according to  claim 10 ,
 wherein the one or more joining structures comprises at least one from the following group of structures, the group consisting of: a solder ball, a solder bump, a pillar, a copper pillar.   
     
     
         13 . The chip package according to  claim 1 , further comprising
 a further joining structure formed on the defined electrically conductive contact region on the chip carrier bottom side;   wherein the defined electrically conductive contact region of the chip carrier is not covered by the further electrically insulating material.   
     
     
         14 . The chip package according to  claim 1 , further comprising
 a further joining structure formed on the defined electrically conductive contact region on the chip carrier bottom side;   wherein the further joining structure is electrically connected to at least one contact pad formed over a chip bottom side.   
     
     
         15 . The chip package according to  claim 14 ,
 wherein the further joining structure comprises at least one from the following group of materials, the group consisting of: a solder, a soft solder, a diffusion solder, an electrically conductive paste, a nanopaste.   
     
     
         16 . The chip package according to  claim 14 ,
 wherein the further joining structure comprises at least one from the following group of structures, the group consisting of: a solder ball, a solder bump, a pillar, a copper pillar.   
     
     
         17 . A chip arrangement comprising:
 a circuit board comprising:
 a through-hole formed in the circuit board; 
 and one or more circuit board contact regions arranged proximate to the through-hole; 
   a chip package arranged within the through-hole,   wherein at least one circuit board contact region is electrically connected to the one or more electrically conductive contact regions formed over a top side of the chip package and in electrical connection with a chip top side; and   wherein at least one further circuit board contact region is electrically connected to a electrically conductive contact region formed over a bottom side of the chip package and in electrical connection with a chip bottom side.   
     
     
         18 . The chip arrangement according to  claim 17 , wherein the chip package further comprises:
 a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip, wherein the one or more electrically conductive contact regions is formed through the electrically insulating material; and   a further electrically insulating material disposed over a chip carrier bottom side wherein the electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.   
     
     
         19 . The chip arrangement according to  claim 17 , wherein the one or more circuit board contact regions are arranged at edges of the through-hole; and
 wherein the chip package is arranged within the through-hole such that the chip top side and the chip bottom side each face opposite edges of the through-hole.   
     
     
         20 . A circuit board comprising:
 a through-hole formed in the circuit board for receiving a chip package;   and one or more circuit board contact regions arranged proximate to the through-hole;   wherein at least one circuit board contact region is configured to be in electrical connection with one or more electrically conductive contact regions formed over a chip package top side and in electrical connection with a chip top side; and   wherein at least one further circuit board contact region is configured to be in electrical connection with an electrically conductive contact region formed over a chip package bottom side and in electrical connection with a chip bottom side.   
     
     
         21 . The circuit board according to  claim 20 , wherein the at least one circuit board contact region and the at least one further circuit board contact region are arranged at substantially opposite edges of the through-hole; and
 wherein the at least one circuit board contact region is configured to face a chip package top side; and   wherein the at least one further circuit board contact region is configured to face a chip package bottom side.   
     
     
         22 . A chip package comprising:
 a chip carrier;   a chip disposed over and electrically connected to a chip carrier first side;   an electrically insulating material disposed over a chip first side and at least partially surrounding the chip;   one or more electrically conductive contact portions formed over the electrically insulating material and in electrical connection with one or more chip pads formed on a chip first side;   a further electrically insulating material disposed over a chip carrier second side, wherein the chip carrier second side faces a direction opposite to the direction which the chip carrier first side faces; and   wherein an electrically conductive contact region on the chip carrier second side is released from the further electrically insulating material.   
     
     
         23 . A method for manufacturing a chip package, the method comprising:
 disposing a chip over a chip carrier top side and electrically connecting the chip to the chip carrier top side;   disposing an electrically insulating material over the chip wherein the electrically insulating material at least partially surrounds the chip;   forming one or more electrically conductive contact regions over the electrically insulating material wherein the one or more electrically conductive contact regions is electrically connected with the chip;   disposing a further electrically insulating material over a chip carrier bottom side;   and releasing an electrically conductive contact region on the chip carrier bottom side from the further electrically insulating material.   
     
     
         24 . A method for manufacturing a chip package, the method comprising:
 disposing a chip over a chip carrier first side and electrically connecting the chip to the chip carrier first side;   disposing an electrically insulating material over the chip first side wherein the electrically insulating material at least partially surrounds the chip;   forming one or more electrically conductive contact regions over the electrically insulating material wherein the one or more electrically conductive contact regions is electrically connected to one or more chip pads formed on the chip first side;   disposing a further electrically insulating material over a chip carrier second side, wherein the chip carrier second side faces a direction opposite to the direction which the chip carrier first side faces; and releasing an electrically conductive contact region on the chip carrier second side from the further electrically insulating material.   
     
     
         25 . A chip arrangement comprising:
 a circuit board comprising:
 a cavity formed in the circuit board; 
 and one or more circuit board contact regions arranged proximate to the cavity; 
   a chip package arranged within the cavity,   wherein at least one circuit board contact region is electrically connected to the one or more electrically conductive contact regions formed over a top side of the chip package and in electrical connection with a chip top side; and   wherein at least one further circuit board contact region is electrically connected to a electrically conductive contact region formed over a bottom side of the chip package and in electrical connection with a chip bottom side.