Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers

Abstract

A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET.

1 . A semiconductor device comprising:
 a substrate;   a fin arranged on the substrate;   a first field effect transistor (FET) comprising:   a first gate stack disposed over a first portion of the fin, the first gate stack including an oxide capping layer disposed on the first portion of the fin, a polysilicon layer disposed on the oxide capping layer, and a silicide material disposed on the polysilicon layer; and   an epitaxial material disposed over second portions of the fin, the epitaxial material defining source and drain regions of the first FET; and   a second field effect transistor (FET) comprising:   a second gate stack disposed over a third portion of the fin, the second gate stack including a conformal high K layer disposed on the second portion of the fin, a metal gate material layer disposed on the conformal high K layer, and a gate conductor material disposed on the metal gate material layer; and   the epitaxial material disposed over fourth portions of the fin, the epitaxial material defining source and drain regions of the second FET.   
     
     
         2 . The device of  claim 1 , further comprising a silicide material disposed on the epitaxial material. 
     
     
         3 . The device of  claim 2 , further comprising a dielectric material layer disposed over portions of the silicide material. 
     
     
         4 . The device of  claim 3 , further comprising a capping material disposed over portions of the first FET, the second FET, and the dielectric material layer. 
     
     
         5 . The device of  claim 4 , further comprising conductive vias communicative with portions of the silicide material of the source and drain regions of the first FET and the second FET. 
     
     
         6 . The device of  claim 1 , further comprising a conductive via communicative with the silicide material disposed on the polysilicon layer of the first FET. 
     
     
         7 . The device of  claim 4 , wherein the capping material includes a layer of nitride material and a layer of oxide material disposed on the layer of nitride material. 
     
     
         8 . The device of  claim 1 , wherein the second FET is a complementary metal oxide semiconductor (CMOS) pFET device. 
     
     
         9 . The device of  claim 1 , wherein the second FET is a complementary metal oxide semiconductor (CMOS) nFET device. 
     
     
         10 . (canceled) 
     
     
         11 . (canceled) 
     
     
         12 . A semiconductor device comprising:
 a substrate;   a fin arranged on the substrate;   a first field effect transistor (FET) comprising:   a first gate stack disposed over a first portion of the fin, the first gate stack including an oxide capping layer disposed on the first portion of the fin, a polysilicon layer disposed on the oxide capping layer, and a silicide material disposed on the polysilicon layer; and   an epitaxial material disposed over second portions of the fin, the epitaxial material defining source and drain regions of the first FET;   a silicide material disposed on the epitaxial material; and   a conductive material disposed over the silicide material;   a second field effect transistor (FET) comprising:   a second gate stack disposed over a third portion of the fin, the second gate stack including a conformal high K layer disposed on the second portion of the fin, a metal gate material layer disposed on the conformal high K layer, and a gate conductor material disposed on the metal gate material layer;   the epitaxial material disposed over fourth portions of the fin, the epitaxial material defining source and drain regions of the second FET;   a silicide material disposed on the epitaxial material; and   a conductive material disposed over the silicide material.   
     
     
         13 . The device of  claim 12 , further comprising a capping material disposed over portions of the first FET and the second FET. 
     
     
         14 . The device of  claim 12 , further comprising a conductive via communicative with the silicide material disposed on the polysilicon layer of the first FET. 
     
     
         15 . The device of  claim 13 , wherein the capping material includes a layer of nitride material and a layer of oxide material disposed on the layer of nitride material. 
     
     
         16 . The device of  claim 13 , wherein the conductive via is partially defined by the capping material. 
     
     
         17 . The device of  claim 12 , wherein the second FET is a complementary metal oxide semiconductor (CMOS) pFET device. 
     
     
         18 . The device of  claim 12 , wherein the second FET is a CMOS nFET device. 
     
     
         19 . (canceled) 
     
     
         20 . (canceled)