Semiconductor structures comprising conductive material lining openings in an insulative material

Abstract

Semiconductor devices have conductive material lining a first opening in an insulative material and in contact with a metal silicide layer at the base of the opening overlying an active area within a silicon material and lining a second opening in the insulative material in direct contact with a polysilicon plug having substantially no metal silicide situated thereon.

1 . A semiconductor device, comprising:
 a conductive material lining a first opening in an insulative material, wherein the conductive material is in contact with a metal silicide material at a base of the first opening overlying an active area within a silicon material, and   the conductive material lining a second opening in the insulative material, wherein the conductive material is in direct contact with a polysilicon plug having substantially no metal silicide situated thereon.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the conductive material comprises, in sequence, a titanium material, a metal nitride, and a conductive metal. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the titanium material comprises nitrogen. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the conductive metal comprises tungsten. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the conductive material overlies the insulative material and electrically interconnects the metal silicide at the base of the first opening with the polysilicon plug in the second opening. 
     
     
         6 . The semiconductor device of  claim 2 , wherein the titanium material is in direct physical contact with the metal silicide layer at the base of the first opening and the polysilicon plug in the second opening. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first opening is in a periphery area of a memory device and the second opening is in a memory cell array area of the memory device. 
     
     
         8 . A semiconductor device, comprising:
 at least one doped polysilicon plug over a substrate;   a metal silicide overlying an active area within a silicon material over the substrate;   an insulative material over at least a portion of the substrate; and   a conductive material in electrical contact with the at least one doped polysilicon plug, the metal silicide, and the insulative material.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the conductive material lines a first opening in the insulative material and wherein a surface of the metal silicide is within the first opening. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the conductive material lines a second opening in the insulative material and wherein a surface of the doped polysilicon plug is within the second opening. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the at least one doped polysilicon plug is substantially free of metal silicide. 
     
     
         12 . The semiconductor device of  claim 8 , wherein the conductive material comprises titanium, a metal nitride over the titanium, and a conductive metal over the metal nitride. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the conductive metal comprises tungsten. 
     
     
         14 . The semiconductor device of  claim 8 , wherein the conductive material overlies at least a portion of the insulative material. 
     
     
         15 . The semiconductor device of  claim 8 , wherein the conductive material comprises nitrogen and titanium. 
     
     
         16 . The device of  claim 8 , wherein the substrate comprises a doped diffusion region proximate the at least one doped polysilicon plug. 
     
     
         17 . The device of  claim 8 , further comprising at least one additional doped polysilicon plug over the substrate, the at least one additional doped polysilicon plug electrically insulated from the conductive material by the insulative material. 
     
     
         18 . A semiconductor device, comprising:
 a first doped polysilicon plug disposed over a first doped diffusion region of a substrate;   a second doped polysilicon plug disposed over a second doped diffusion region of the substrate;   a metal silicide overlying an active area within a silicon material over the substrate;   an insulative material over the second doped polysilicon plug and at least a portion of the substrate; and   a conductive material in electrical contact with the first doped polysilicon plug, the metal silicide, and the insulative material and insulated from the second doped polysilicon plug.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising a memory cell disposed over the substrate and between the first doped polysilicon plug and the second doped polysilicon plug. 
     
     
         20 . The semiconductor device of  claim 18 , wherein the first doped polysilicon plug is in electrical contact with a bit line. 
     
     
         21 . The semiconductor device of  claim 18 , wherein a portion of the conductive material is in electrical contact with the first doped polysilicon plug, and another, discontinuous portion of the conductive material is in electrical contact with the metal silicide.