Memory Device with Charge Trap

Abstract

A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

1 - 20 . (canceled) 
     
     
         21 . A memory system comprising:
 a first insulator layer over a semiconductor substrate;   a charge trap layer over the first insulator layer;   an intermediate layer over the charge trap layer; and   a second insulator layer formed over the intermediate layer.   
     
     
         22 . The memory system of  claim 21  wherein the charge trap layer includes a silicon rich nitride. 
     
     
         23 . The memory system of  claim 21  wherein the intermediate layer includes a regular silicon nitride or a silicon rich nitride. 
     
     
         24 . The memory system of  claim 21  wherein the second insulator layer includes an upper portion of the intermediate layer oxidized. 
     
     
         25 . The memory system of  claim 21  further comprising:
 a memory system with memory cell systems; and 
 a device or an electronic system with the memory system. 
 
     
     
         26 . The memory system of  claim 21  wherein:
 the first insulator layer is a first dielectric layer over the semiconductor substrate; 
 the charge trap layer is a silicon rich nitride layer over the first insulator layer; 
 the intermediate layer includes a nitride over the charge trap layer; and 
 the second insulator layer is a second dielectric layer formed over the intermediate layer. 
 
     
     
         27 . The memory system of  claim 26  wherein the second dielectric layer over the intermediate layer includes a pinhole filled in the intermediate layer for reduction of charge loss through the first dielectric layer and the second dielectric layer. 
     
     
         28 . The memory system of  claim 26  wherein the second dielectric layer over the intermediate layer includes the entire thickness of the intermediate layer oxidized. 
     
     
         29 . The memory system of  claim 26  wherein the intermediate layer includes a gradient concentration of the silicon rich nitride layer. 
     
     
         30 . The memory system of  claim 26  further comprising a gate contact over the second dielectric layer. 
     
     
         31 . A memory device comprising:
 a first insulator layer over a semiconductor substrate;   a charge trap layer over the first insulator layer;   an intermediate layer over the charge trap layer;   a second insulator layer;   wherein the charge trap layer comprises a first material and the intermediate layer comprises a second material, wherein the first material is situated adjacent to the first insulator layer and the second material is situated adjacent to the second insulator layer.   
     
     
         32 . The memory device of  claim 31  wherein a charge-storage bi-layer is formed by the charge trap layer and the intermediate layer, the charge-storage bi-layer having increased data retention. 
     
     
         33 . The memory device of  claim 31  wherein the charge trap layer includes silicon rich nitride. 
     
     
         34 . The memory device of  claim 31  wherein the intermediate layer includes stoichiometric silicon nitride. 
     
     
         35 . The memory device of  claim 31  wherein the second insulator layer is formed by steam oxidizing the intermediate layer. 
     
     
         36 . The memory device of  claim 31  wherein the second insulator layer is formed by steam oxidizing the intermediate layer including filling a pinhole in the intermediate layer. 
     
     
         37 . The memory device of  claim 31  wherein the second insulator layer is formed by steam oxidizing the intermediate layer including oxidizing the entire thickness of the intermediate layer. 
     
     
         38 . The memory device of  claim 31  further comprising forming a gate contact over the second insulator layer.