Static random access memory cell with single-sided buffer and asymmetric construction

Abstract

Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

What is claimed is: 
     
         1 . A memory cell formed in a contiguous bit cell area of an integrated circuit, comprising:
 a first inverter comprised of a first transistor, the first inverter having an output at a first storage node and an input coupled to a second storage node;   a second inverter comprised of a second transistor, the second inverter having an output at the second storage node and an input coupled to the first storage node, the second transistor serving a circuit function in the second inverter that is the same as the circuit function served by the first transistor in the first inverter; and   a buffer circuit disposed within the bit cell area nearer to the first inverter than to the second inverter;   wherein the first transistor has a physical construction different from the second transistor.   
     
     
         2 . The memory cell of  claim 1 , wherein the first transistor is disposed in the bit cell area of the memory cell between the buffer circuit and the second transistor. 
     
     
         3 . The memory cell of  claim 1 , wherein the first inverter comprises:
 a first load and a first driver transistor, the first driver transistor having a source/drain path connected on one side to the first load at the first storage node, and having a gate connected to the second storage node;   wherein the second inverter comprises:
 a second load and a second driver transistor, the second driver transistor having a source/drain path connected on one side to the second load at the second storage node, and having a gate connected to the first storage node; 
   and wherein the first transistor corresponds to the first driver transistor, and the second transistor corresponds to the second driver transistor.   
     
     
         4 . The memory cell of  claim 1 , wherein the first inverter comprises:
 a first load transistor and a first driver transistor, the first load and first driver transistors having source/drain paths in series and connected together at the first storage node, and the first load and first driver transistors each having a gate connected to the second storage node;   wherein the second inverter comprises:
 a second load transistor and a second driver transistor, the second load and second driver transistors having source/drain paths in series and connected together at the second storage node, and the second load and second driver transistors each having a gate connected to the first storage node; 
   and wherein the first transistor corresponds to the first load transistor, and the second transistor corresponds to the second load transistor.   
     
     
         5 . The memory cell of  claim 4 , wherein the first driver transistor also has a physical construction different from the second driver transistor. 
     
     
         6 . The memory cell of  claim 1 , wherein each memory cell further comprises:
 a first pass transistor having a source/drain path connected on one side to the first storage node and having a gate connected to a word line; and   a second pass transistor having a source/drain path connected on one side to the second storage node and having a gate connected to the word line;   wherein the first pass transistor also has a physical construction different from the second pass transistor.   
     
     
         7 . The memory cell of  claim 1 , wherein the buffer circuit comprises:
 a first buffer transistor having a source/drain path connected on one side to a read bit line, and having a gate connected to a read word line; and   a second buffer transistor having a source/drain path in series with the source/drain path of the first buffer transistor between a read bit line and a reference voltage, and having a gate connected to one of the storage nodes;   wherein at least one of the first and second buffer transistors is constructed with feature sizes that are larger than corresponding feature sizes of the first and second transistors.   
     
     
         8 . The memory cell of  claim 7 , wherein the gate of the second buffer transistor is connected to the second storage node. 
     
     
         9 . The memory cell of  claim 1 , wherein the first and second transistors differ from one another in construction by one or more attributes selected from the group consisting of channel width, channel length, and net channel dopant concentration. 
     
     
         10 . The memory cell of  claim 9 , wherein the buffer circuit reduces source/drain drive strength of the first transistor; and wherein the first transistor is constructed to have, relative to the second transistor, one or more of the attributes selected from the group consisting of a larger channel width, a shorter channel length, and a lower net channel dopant concentration. 
     
     
         11 . The memory cell of  claim 9 , wherein the buffer circuit increases source/drain drive strength of the first transistor; and wherein the first transistor is constructed to have, relative to the second transistor, one or more of the attributes selected from the group consisting of a smaller channel width, a longer channel length, and a higher net channel dopant concentration. 
     
     
         12 . A memory in an integrated circuit, comprising:
 an array of memory cells, each memory cell formed in a contiguous bit cell area of the integrated circuit, each memory cell comprising:
 a first inverter comprised of a first transistor, the first inverter having an output at a first storage node and an input coupled to a second storage node; 
 a second inverter comprised of a second transistor, the second inverter having an output at the second storage node and an input coupled to the first storage node, the second transistor serving a circuit function in the second inverter that is the same as the circuit function served by the first transistor in the first inverter; 
 a first pass transistor having a source/drain path connected between the first storage node and a first write bit line for the column including the memory cell, and having a gate connected to a write word line for the row including the memory cell; 
 a second pass transistor having a source/drain path connected between the second storage node and a second write bit line for the column including the memory cell, and having a gate connected to the write word line; and 
 a buffer circuit disposed within the bit cell area nearer to the first inverter than to the second inverter, and comprising:
 a first buffer transistor having a source/drain path, and having a gate connected to a read word line for the row including the memory cell; and 
 a second buffer transistor having a source/drain path in series with the source/drain path of the first buffer transistor between a read bit line for the column including the memory cell and a reference voltage, and having a gate connected to the second storage node; and 
 
   peripheral circuitry, disposed adjacent to the array, for accessing one or more selected memory cells in the array;   wherein at least one of the first and second buffer transistors in each memory cell is constructed with feature sizes that are substantially larger than corresponding feature sizes of the first and second transistors;   and wherein, in each memory cell, the first transistor has a physical construction different from the second transistor.   
     
     
         13 . The memory of  claim 12 , wherein adjacent memory cells in the array are disposed in adjacent bit cell areas to one another;
 wherein the first transistor in each memory cell is disposed between the buffer circuit and the second transistor of its memory cell;   and wherein the second transistor of each of first and second adjacent memory cells is disposed between the first transistor of its memory cell and the second transistor of the other of the first and second adjacent memory cells.   
     
     
         14 . The memory of  claim 12 , wherein the first inverter of each memory cell comprises:
 a first load and a first driver transistor, the first driver transistor having a source/drain path connected on one side to the first load at the first storage node, and having a gate connected to the second storage node;   wherein the second inverter of each memory cell comprises:   a second load and a second driver transistor, the second driver transistor having a source/drain path connected on one side to the second load at the second storage node, and having a gate connected to the first storage node;   and wherein the first transistor corresponds to the first driver transistor, and the second transistor corresponds to the second driver transistor.   
     
     
         15 . The memory of  claim 12 , wherein the first inverter of each memory cell comprises:
 a first load transistor and a first driver transistor, the first load and first driver transistors having source/drain paths in series and connected together at the first storage node, and the first load and first driver transistors each having a gate connected to the second storage node;   wherein the second inverter of each memory cell comprises:   a second load transistor and a second driver transistor, the second load and second driver transistors having source/drain paths in series and connected together at the second storage node, and the second load and second driver transistors each having a gate connected to the first storage node;   and wherein the first transistor corresponds to the first load transistor, and the second transistor corresponds to the second load transistor.   
     
     
         16 . The memory of  claim 15 , wherein the first driver transistor also has a physical construction different from the second driver transistor. 
     
     
         17 . The memory of  claim 12 , wherein the first pass transistor also has a physical construction different from the second pass transistor. 
     
     
         18 . The memory of  claim 12 , wherein the first and second transistors of each memory cell differ from one another in construction by one or more attributes selected from the group consisting of channel width, channel length, and net channel dopant concentration. 
     
     
         19 . The memory of  claim 18 , wherein the buffer circuit reduces source/drain drive strength of the first transistor; and wherein, for each memory cell, the first transistor is constructed to have, relative to the second transistor, one or more of the attributes selected from the group consisting of a larger channel width, a shorter channel length, and a lower net channel dopant concentration. 
     
     
         20 . The memory of  claim 18 , wherein the buffer circuit increases source/drain drive strength of the first transistor; and wherein, for each memory cell, the first transistor is constructed to have, relative to the second transistor, one or more of the attributes selected from the group consisting of a smaller channel width, a longer channel length, and a higher net channel dopant concentration.