Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate

Abstract

In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

What is claimed is: 
     
         1 . An integrated high performance combinatorial processing system, comprising:
 a transfer chamber supporting a plurality of modules, wherein vacuum is maintained within the transfer chamber and the plurality of modules;   a first processing module configured to deposit a first layer on a first test structure formed within a first region of a substrate, the substrate having multiple regions that are electrically isolated from one another; and   a second processing module configured to deposit a second layer on the first layer;   wherein at least the first layer or the second layer is varied across multiple regions of the substrate; and   wherein a single physical mask is used to deposit both the first layer and the second layer.   
     
     
         2 . The combinatorial processing system of  claim 1 , wherein the first processing module or the second processing module is a physical vapor deposition module. 
     
     
         3 . The combinatorial processing system of  claim 1 , wherein the first processing module or the second processing module further comprises a shutter garage with moveable shutters that enable combinatorial processing. 
     
     
         4 . The combinatorial processing system of  claim 1 , wherein the first and second processing modules are the same module. 
     
     
         5 . The combinatorial processing system of  claim 1 , further comprising a library module housing a plurality of processing masks for use in at least one other processing module. 
     
     
         6 . The combinatorial processing system of  claim 1 , further comprising a controller operably connected to the first and second processing modules. 
     
     
         7 . The combinatorial processing system of  claim 1 , further comprising:
 a first controller operably connected to the first processing module; and   a second controller operably connected to the second processing module.   
     
     
         8 . The combinatorial processing system of  claim 1 , wherein the first processing module or the second processing module is a wet deposition module. 
     
     
         9 . The combinatorial processing system of  claim 8 , wherein the wet processing module comprises an electroless deposition or an electrochemical deposition module. 
     
     
         10 . The combinatorial processing system of  claim 1 , wherein the first layer comprises an insulating layer. 
     
     
         11 . The combinatorial processing system of  claim 1 , wherein the second layer comprises a conductive layer. 
     
     
         12 . The combinatorial processing system of  claim 1 , wherein a material of at least the first layer or the second layer is varied across multiple regions of the substrate. 
     
     
         13 . The combinatorial processing system of  claim 1 , wherein a unit process of at least the first layer or the second layer is varied across multiple regions of the substrate. 
     
     
         14 . The combinatorial processing system of  claim 1 , wherein a process sequence of at least the first layer or the second layer is varied across multiple regions of the substrate. 
     
     
         15 . The combinatorial processing system of  claim 1 , wherein a process condition of at least the first layer or the second layer is varied across multiple regions of the substrate. 
     
     
         16 . The combinatorial processing system of  claim 1 , wherein one of the first layer or the second layer is uniform across the substrate. 
     
     
         17 . The combinatorial processing system of  claim 1 , wherein the single physical mask comprises a shadowmask configured for clamping to the substrate. 
     
     
         18 . The combinatorial processing system of  claim 1 , wherein the single physical mask comprises a first marking configured for alignment with a second marking on the substrate.