US2014117511A1PendingUtilityA1

Passivation Layer and Method of Making a Passivation Layer

45
Assignee: INFINEON TECHNOLOGIES AGPriority: Oct 30, 2012Filed: Oct 30, 2012Published: May 1, 2014
Est. expiryOct 30, 2032(~6.3 yrs left)· nominal 20-yr term from priority
H10P 70/23H10P 14/69215H10P 14/6927H10P 14/6532H10P 14/6528H10P 14/6336H10P 14/662H10W 74/43H10W 20/071H10W 74/137
45
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for manufacturing a passivation layer, the method comprising:
 depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen; and   depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.   
     
     
         2 . The method according to  claim 1 , wherein depositing the first and second silicon based dielectric layers comprises a plasma enhanced CVD (PE-CVD). 
     
     
         3 . The method according to  claim 1 , wherein the first silicon based dielectric layer comprises SiO x N y . 
     
     
         4 . The method according to  claim 1 , wherein the second silicon based dielectric layer comprises SiO x . 
     
     
         5 . The method according to  claim 1 , wherein the first silicon based dielectric layer is about 100 nm to about 1000 nm thick and wherein the second silicon based dielectric layer is about 100 nm to about 2000 nm thick. 
     
     
         6 . A method for manufacturing a layer stack, the method comprising:
 placing a workpiece in a process chamber;   providing a first set of process gases for depositing a SiO x N y  layer; and   without interrupting a plasma power, changing the first set of process gases to a second set of process gases thereby forming a SiO x  layer on the SiO x N y  layer.   
     
     
         7 . The method according to  claim 6 , wherein the first set of process gases comprises providing SiH 4 , N 2 O, NH 3  and N 2  or an inert gas. 
     
     
         8 . The method according to  claim 6 , wherein the second set of process gases comprises turning on SiH 4 , N 2 O or both with an inert gas. 
     
     
         9 . The method according to  claim 6 , wherein a pressure is set between about 1 Torr and about 10 Torr. 
     
     
         10 . A method for manufacturing a layer stack, the method comprising:
 placing a workpiece in a process chamber;   turning on a first set of process gases for depositing a SiO x N y  layer,   plasma-cleaning the workpiece; and   depositing a dielectric layer on the SiO x N y  layer.   
     
     
         11 . The method according to  claim 10 , wherein depositing the dielectric layer comprises a silicon based layer. 
     
     
         12 . The method according to  claim 10 , wherein depositing the dielectric layer comprises turning on a second set of process gases for depositing a SiO x  layer. 
     
     
         13 . The method according to  claim 12 , wherein turning on the second set of process gases comprising SiH 4 , N 2 O or both with an inert gas. 
     
     
         14 . The method according to  claim 13 , wherein turning on the first set of process gases comprising SiH 4 , N 2 O, NH 3  and N 2 . 
     
     
         15 . The method according to  claim 14 , wherein cleaning the workpiece comprises applying an N 2 O plasma including a second inert gas. 
     
     
         16 . A semiconductor device comprising
 a workpiece;   a silicon oxynitride layer (SiO x N y ) disposed on the workpiece;   a silicon oxide layer (SiO x ) disposed on the silicon oxynitride layer; and   a transition layer between the silicon oxynitride layer and the silicon oxide layer, wherein the transition layer comprises silicon, oxygen and nitrogen, wherein a concentration of nitrogen in the silicon oxynitride layer is different than a concentration of nitrogen in the transition layer.   
     
     
         17 . The semiconductor device according to  claim 16 , wherein the concentration of nitrogen in the transition layer is higher in a lower region adjacent to the silicon oxynitride layer and lower in an upper region adjacent to the silicon oxide layer. 
     
     
         18 . The semiconductor device according to  claim 17 , wherein the concentration of nitrogen gradually changes over a thickness of the transition layer. 
     
     
         19 . The semiconductor device according to  claim 16 , wherein the transition layer is disposed directly on the silicon oxynitride layer and wherein the silicon oxide layer is disposed directly on the transition layer. 
     
     
         20 . The semiconductor device according to  claim 16 , wherein the transition layer is a thin layer.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.