Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (tsvs)

Abstract

Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW 2 O 8 ) or hafnium tungstate (HfW 2 O 8 ). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

1 - 30 . (canceled) 
     
     
         31 . An integrated circuit comprising:
 a substrate having a through-hole formed therein;   an electrically conductive material disposed within the through-hole, wherein the electrically conductive material provides an electrical connection between a first surface and a second surface of the substrate; and   a negative thermal expansion (NTE) material disposed within the through-hole between the substrate and the electrically conductive material.   
     
     
         32 . The integrated circuit of  claim 31 , wherein the substrate comprises silicon, germanium, III-V material, oxide, nitride, or combinations thereof. 
     
     
         33 . The integrated circuit of  claim 31 , wherein the through-hole has an aspect ratio greater than or equal to about 1:10. 
     
     
         34 . The integrated circuit of  claim 31 , wherein the NTE material comprises zirconium tungstate (ZrW 2 O 8 ). 
     
     
         35 . The integrated circuit of  claim 31 , wherein the NTE material comprises hafnium tungstate (HfW 2 O 8 ). 
     
     
         36 . The integrated circuit of  claim 31  further comprising a capacitance layer disposed between the substrate and the NTE material. 
     
     
         37 . The integrated circuit of  claim 36 , wherein the capacitance layer comprises silicon dioxide. 
     
     
         38 . The integrated circuit of  claim 31 , wherein the integrated circuit is configured to align with another substrate, chip, layer, die, and/or integrated circuit to form a three-dimensional integrated circuit or other three-dimensional package. 
     
     
         39 . The integrated circuit of  claim 31 , wherein the NTE material provides a barrier that protects against at least one of leakage, voltage breakdown, and/or diffusion of the electrically conductive material. 
     
     
         40 . The integrated circuit of  claim 31 , further comprising a seed layer of the electrically conductive material. 
     
     
         41 . A method comprising:
 forming a through-hole in a substrate;   depositing a negative thermal expansion (NTE) material on an interior surface of the through-hole; and   filling the through-hole with an electrically conductive material, wherein the electrically conductive material provides an electrical connection between a first surface and a second surface of the substrate.   
     
     
         42 . The method of  claim 41 , wherein the through-hole has an aspect ratio greater than or equal to about 1:10. 
     
     
         43 . The method of  claim 41 , wherein the NTE material comprises zirconium tungstate (ZrW 2 O 8 ) or hafnium tungstate (HfW 2 O 8 ). 
     
     
         44 . The method of  claim 41 , wherein the NTE material is deposited by atomic layer deposition, chemical vapor deposition, and/or physical vapor deposition. 
     
     
         45 . The method of  claim 41 , wherein the electrically conductive material is deposited by electroplating or electroless deposition. 
     
     
         46 . The method of  claim 41  further comprising depositing a seed layer of the electrically conductive material prior to filling the through-hole with the electrically conductive material. 
     
     
         47 . The method of  claim 41  further comprising forming a capacitance layer between the substrate and the NTE material. 
     
     
         48 . The method of  claim 47 , wherein the capacitance layer comprises silicon dioxide. 
     
     
         49 . An integrated circuit fabricated using the method of  claim 41 . 
     
     
         50 . An electronic device comprising one or more of the integrated circuit of  claim 49 . 
     
     
         51 . The electronic device of  claim 50 , wherein the device comprises at least one of a memory circuit, a communication chip, a processor, and/or a computing system. 
     
     
         52 . An integrated circuit comprising:
 a silicon substrate having a through-hole formed therein;   a quantity of copper disposed within the through-hole, wherein the copper provides an electrical connection between a first surface and a second surface of the silicon substrate; and   a negative thermal expansion (NTE) material disposed within the through-hole between the silicon substrate and the copper.   
     
     
         53 . The integrated circuit of  claim 52 , wherein the through-hole has an aspect ratio greater than or equal to about 1:10, and the NTE material reduces radial stress in the through-hole. 
     
     
         54 . The integrated circuit of  claim 52 , wherein the NTE material comprises zirconium tungstate (ZrW 2 O 8 ) or hafnium tungstate (HfW 2 O 8 ). 
     
     
         55 . The integrated circuit of  claim 52  further comprising a capacitance layer disposed between the silicon substrate and the NTE material, wherein the capacitance layer comprises silicon dioxide.