Finfet with merge-free fins

Abstract

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

1 . A semiconductor device having a gate region, comprising:
 an insulation layer extending along a first direction to define a length and a second direction perpendicular to the first direction to define a width, the insulation layer having a gate insulation region disposed between first and second non-gate insulation regions different from the gate insulation region;   an active semiconductor layer formed on the insulation layer; and   a plurality of fins formed on the gate insulation region and between the first and second non-gate insulation regions.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the gate insulation region has a gate pocket that isolates the plurality of fins from the first and second non-gate insulation regions. 
     
     
         3 . The semiconductor device of  claim 2 , further comprising a masking layer formed on an upper surface of the active semiconductor layer, the gate pocket formed through the masking layer and the active semiconductor layer to expose the insulation layer. 
     
     
         4 . The semiconductor device of  claim 3 , wherein each fin among the plurality of fins extends along the first direction to define a fin length not exceeding a length of the gate insulation region. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the plurality of fins are arranged along the second direction of the insulation layer. 
     
     
         6 . The semiconductor device of  claim 3 , further comprising a gate stack disposed in the gate pocket and covering the plurality of fins. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the gate stack further comprises a gate insulation layer formed of a high-k material. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the gate stack further comprises an electrode coupled to the gate insulation layer. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the first non-gate insulation region is a source region and the second non-gate insulation region is a drain region. 
     
     
         10 .- 30 . (canceled)