Faceted semiconductor nanowire

Abstract

Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 forming a semiconductor fin including a single crystalline semiconductor material on a top surface of an insulator layer; and   forming a semiconductor nanowire by growing a plurality of faceted semiconductor material portions on said semiconductor fin until all physically exposed surfaces of said semiconductor nanowire become faceted surfaces that contact one another or one or more dielectric surfaces.   
     
     
         2 . The method of  claim 1 , wherein said semiconductor fin includes a pair of vertical sidewalls that extend along a lengthwise direction of said semiconductor fin, and said plurality of faceted semiconductor material portions are formed on all surfaces of said pair of vertical sidewalls. 
     
     
         3 . The method of  claim 1 , further comprising forming a gate stack structure across said semiconductor nanowire, wherein said gate stack structure includes a stack of a gate dielectric and a gate electrode. 
     
     
         4 . The method of  claim 3 , further comprising forming a source region and a drain region within end portions of said semiconductor nanowire, wherein said source region and said drain region are laterally spaced from each other by a body region underlying said gate stack structure. 
     
     
         5 . The method of  claim 3 , wherein said plurality of faceted semiconductor material portions is under a compressive strain or under a tensile strain. 
     
     
         6 . The method of  claim 1 , further comprising growing a semiconductor shell region from all of said physically exposed surfaces of said semiconductor nanowire by depositing an additional semiconductor material thereupon. 
     
     
         7 . The method of  claim 6 , wherein said growing of said semiconductor shell region is performed employing a process condition that causes said additional semiconductor material to grow in a direction perpendicular to said faceted surfaces. 
     
     
         8 . The method of  claim 6 , wherein said semiconductor shell region is under a compressive strain or under a tensile strain.