Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability

Abstract

A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

What is claimed is: 
     
         1 . A device comprising:
 a substrate;   a plurality of trench isolation regions formed within the substrate;   a tunneling dielectric layer disposed on the substrate, the tunneling dielectric layer further disposed between and in contact with the plurality of trench isolation regions;   a composite nitride layer including a silicon-nitride (SiN) layer disposed on a silicon-rich nitride (SiRN) layer, the composite nitride layer disposed on the tunneling dielectric layer, and further disposed between and in contact with the plurality of trench isolation regions; and   an oxide layer formed by oxidation of a portion of the silicon nitride layer, wherein the SiN layer has a thickness that precludes exposure of any portion of the SiRN layer to the oxide layer.   
     
     
         2 . The device of  claim 1 , further comprising:
 a polysilicon region disposed on the oxide layer.   
     
     
         3 . The device of  claim 1 , wherein the tunneling dielectric layer comprises silicon dioxide. 
     
     
         4 . The device of  claim 1 , wherein a thickness of the tunneling dielectric layer is approximately 6 nm. 
     
     
         5 . The device of  claim 1 , wherein a thickness of the SiRN layer is approximately 9 nm. 
     
     
         6 . The device of  claim 1 , wherein the SiRN layer has an extinction coefficient in the range of approximately 0.9 through 1.19. 
     
     
         7 . The device of  claim 1 , wherein the substrate comprises at least one of silicon, germanium, and silicon-germanium. 
     
     
         8 . The device of  claim 1 , wherein the device further comprises:
 a channel region beneath the tunneling dielectric layer; and   a drain region and a source region, wherein the drain region and the channel region are each adjacent to the channel region.   
     
     
         9 . The device of  claim 1 , wherein the device forms a part of a NAND flash memory cell array. 
     
     
         10 . The device of  claim 1 , wherein the device forms a part of a NOR flash memory cell array. 
     
     
         11 . A charge trapping flash memory apparatus, comprising:
 an array of semiconductor device cells formed on a substrate, wherein each semiconductor device cell comprises:   a plurality of trench isolation regions formed within the substrate;   a tunneling dielectric layer disposed on the substrate, the tunneling dielectric layer further disposed between and in contact with the plurality of trench isolation regions;   a composite nitride layer including a silicon-nitride (SiN) layer disposed on a silicon-rich nitride (SiRN) layer, the composite nitride layer disposed on the tunneling dielectric layer, and further disposed between and in contact with the plurality of trench isolation regions; and   an oxide layer formed by oxidation of a portion of the silicon nitride layer, wherein the SiN layer has a thickness that precludes exposure of any portion of the SiRN layer to the oxide layer.   
     
     
         12 . The apparatus of  claim 11 , further comprising:
 a polysilicon region disposed on the oxide layer.   
     
     
         13 . The apparatus of  claim 11 , wherein the tunneling dielectric layer comprises silicon dioxide. 
     
     
         14 . The apparatus of  claim 11 , wherein a thickness of the tunneling dielectric layer is approximately 6 nm. 
     
     
         15 . The apparatus of  claim 11 , wherein a thickness of the SiRN layer is approximately 9 nm. 
     
     
         16 . The apparatus of  claim 11 , wherein the SiRN layer has an extinction coefficient in the range of approximately 0.9 through 1.19. 
     
     
         17 . The apparatus of  claim 11 , wherein the substrate comprises at least one of silicon, germanium, and silicon-germanium. 
     
     
         18 . The apparatus of  claim 11 , wherein each semiconductor device cell further comprises:
 a channel region beneath the tunneling dielectric layer; and   a drain region and a source region, wherein the drain region and the channel region are each adjacent to the channel region.   
     
     
         19 . The apparatus of  claim 11 , wherein the array of semiconductor device cells forms a part of a NAND flash memory cell array. 
     
     
         20 . The apparatus of  claim 11 , wherein the array of semiconductor device cells forms a part of a NOR flash memory cell array.