Integrated circuit and method of manufacturing the same

Abstract

Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

1 - 6 . (canceled) 
     
     
         7 . A wafer level chip scale package, WLCSP, comprising a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die,
 wherein the electrically conductive RDL defines a signal routing circuit and forms an electrically conductive ring surrounding the signal routing circuit,
 wherein underlying the electrical conductive RDL, etched trenches in the die surround the signal routing circuit, and 
   wherein the side and lower surfaces of the die are coated with an electrically conductive shielding material such that the electrically conductive shielding material contacts at least a portion of the periphery of the conductive ring   
     
     
         8 . The WLCSP of  claim 7 , wherein the electrically conductive shielding material is an electroless metal. 
     
     
         9 . The WLCSP of  claim 8 , wherein the electroless metal is an electroless nickel.