Multilevel Leadframe

Abstract

A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together.

What is claimed is: 
     
         1 - 15 . (canceled) 
     
     
         16 . A multilevel leadframe for an integrated circuit package, the leadframe comprising:
 a plurality of lead lines formed in a first level of the multilevel leadframe, each lead line having a line width and being separated from an adjacent lead line by at least a lead line clearance distance;   a first plurality of bond pads formed in a second level of the multilevel leadframe arranged in a first row and being separated from an adjacent bond pad by a bond pad clearance distance, each bond pad having a pad width and wherein the pad width is greater than the line width; and   a second plurality of bond pads arranged in a second row, wherein each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.   
     
     
         17 . The multilevel leadframe of  claim 16 , wherein the bond pad clearance distance is less than twice the lead line clearance distance. 
     
     
         18 . The multilevel leadframe of  claim 16 , wherein the bond pad clearance distance approximately equal to the lead line clearance distance. 
     
     
         19 . The multilevel leadframe of  claim 16 , wherein the leadframe has a leadframe thickness, and wherein the bond pad clearance distance is approximately equal to the leadframe thickness. 
     
     
         20 . The multilevel leadframe of  claim 16 , further comprising a plurality of substrate contacts coupled to the lead lines, wherein the plurality of substrate contacts are arranged around a periphery of the multilevel lead frame to form a die cavity sufficiently deep to surround a die when the die is attached to the first and second plurality of bond pads. 
     
     
         21 . A method for forming a multilevel leadframe for an integrated circuit, the method comprising:
 etching a conductive sheet from one side to from a thinner region within a frame region for leads lines and bond pads;   etching the conductive sheet to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row, each bond pad having a pad width and being separated from an adjacent bond pad by a bond pad clearance distance; and   etching the conductive sheet from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and being separated from an adjacent lead line by at least a lead line clearance distance,   wherein each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.   
     
     
         22 . The method of  claim 21 , wherein the bond pad clearance distance is less than twice the lead line clearance distance. 
     
     
         23 . The method of  claim 21 , wherein the bond pad clearance distance approximately equal to the lead line clearance distance. 
     
     
         24 . The method of  claim 21 , wherein the thinner region has a leadframe thickness, and wherein the bond pad clearance distance is approximately equal to the leadframe thickness. 
     
     
         25 . The method of  claim 21 , wherein etching a conductive sheet from one side to from a thinner region also forms a die cavity within the multilevel leadframe. 
     
     
         26 . A packaged integrated circuit comprising:
 an integrated circuit die having a plurality of input/output terminals;   a multilevel leadframe bond pats bonded to the plurality of input/output terminals, the leadframe comprising:
 a plurality of lead lines formed in a first level of the multilevel leadframe, each lead line having a line width and being separated from an adjacent lead line by at least a lead line clearance distance; 
   a first plurality of bond pads formed in a second level of the multilevel leadframe arranged in a first row and being separated from an adjacent bond pad by a bond pad clearance distance, each bond pad having a pad width and wherein the pad width is greater than the line width; and   a second plurality of bond pads arranged in a second row, wherein each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.   
     
     
         27 . The packaged integrated circuit of  claim 26 , wherein the bond pad clearance distance is less than twice the lead line clearance distance. 
     
     
         28 . The packaged integrated circuit of  claim 26 , wherein the bond pad clearance distance approximately equal to the lead line clearance distance. 
     
     
         29 . The multilevel leadframe of  claim 26 , wherein the leadframe has a leadframe thickness, and wherein the bond pad clearance distance is approximately equal to the leadframe thickness. 
     
     
         30 . The packaged integrated circuit of  claim 26 , further comprising a plurality of substrate contacts coupled to the lead lines, wherein the plurality of substrate contacts are arranged around a periphery of the multilevel lead frame to form a die cavity sufficiently deep to surround the integrated circuit die.