Co-integration of elemental semiconductor devices and compound semiconductor devices

Abstract

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.

What is claimed is: 
     
         1 . A semiconductor structure comprising
 at least one dielectric bonding material layer located on a handle substrate; and   a first epitaxial semiconductor portion and a second epitaxial semiconductor portion, wherein one of said first and second epitaxial semiconductor portions comprises a single crystalline elemental semiconductor material, and another of said first and second epitaxial semiconductor portions comprises a single crystalline compound semiconductor material, wherein said at least one dielectric bonding material layer comprises:   a first dielectric bonding material layer not contacting said first and second epitaxial semiconductor portions; and   a second dielectric bonding material layer underlying all of said first dielectric bonding material layer and contacting said first epitaxial semiconductor portion.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 a first field effect transistor located on said handle substrate, wherein said first epitaxial semiconductor portion comprises a body region, a source region, and a drain region of said first field effect transistor; and   a second field effect transistor located on said handle substrate, wherein said second epitaxial semiconductor portion comprises a body region, a source region, and a drain region of said second field effect transistor.   
     
     
         3 . The semiconductor structure of  claim 2 , wherein one of said first and second field effect transistors is a p-type field effect transistor, and another of said first and second field effect transistors is an n-type field effect transistor, and wherein a body region, a source region, and a drain region of said n-type field effect transistor includes said single crystalline compound semiconductor material, and a body region, a source region, and a drain region of said p-type field effect transistor includes said single crystalline elemental semiconductor material. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein said first field effect transistor comprises a first capping semiconductor material portion in contact with a top surface of, and in epitaxial alignment with, said first epitaxial semiconductor portion, and said second field effect transistor comprises a second capping semiconductor material portion in contact with a top surface of, and in epitaxial alignment with, said second epitaxial semiconductor portion, wherein said first and second capping semiconductor material portions have a same thickness. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein said single crystalline elemental semiconductor material is selected from single crystalline silicon, single crystalline germanium, a single crystalline silicon-germanium alloy, a single crystalline silicon-carbon alloy, and a single crystalline silicon-germanium-carbon alloy. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said single crystalline compound semiconductor material is selected from a III-V compound semiconductor material and a II-V compound semiconductor material. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein said handle substrate is selected from a bulk semiconductor substrate, a semiconductor-on-insulator substrate, a stack of at least two semiconductor material layers having different compositions and epitaxially aligned to one another, an insulator substrate, a metallic substrate, and a plastic substrate. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein said first dielectric bonding material layer has a same composition as said second first dielectric bonding material layer. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein said first dielectric bonding material layer has a different composition as said second first dielectric bonding material layer. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein said first and second epitaxial semiconductor portions have different thicknesses. 
     
     
         11 . The semiconductor structure of  claim 1 , wherein said at least one dielectric bonding material layer further comprises a third dielectric bonding material layer underlying all of said first dielectric bonding material layer and all of said second dielectric bonding material layer and contacting said second epitaxial semiconductor portion. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein said first dielectric bonding material layer has a first composition, said second dielectric bonding material layer has a second composition, and said third dielectric bonding material layer has a third composition, and at least one of said first, second, and third compositions is different from another of said first, second, and third compositions. 
     
     
         13 . The semiconductor structure of  claim 11 , further comprising:
 a first field effect transistor located on said handle substrate, wherein said first epitaxial semiconductor portion comprises a body region, a source region, and a drain region of said first field effect transistor; and   a second field effect transistor located on said handle substrate, wherein said second epitaxial semiconductor portion comprises a body region, a source region, and a drain region of said second field effect transistor.   
     
     
         14 . The semiconductor structure of  claim 13 , wherein one of said first and second field effect transistors is a p-type field effect transistor, and another of said first and second field effect transistors is an n-type field effect transistor, and wherein a body region, a source region, and a drain region of said n-type field effect transistor includes said single crystalline compound semiconductor material, and a body region, a source region, and a drain region of said p-type field effect transistor includes said single crystalline elemental semiconductor material. 
     
     
         15 . The semiconductor structure of  claim 13 , wherein said first field effect transistor comprises a first capping semiconductor material portion in contact with a top surface of, and in epitaxial alignment with, said first epitaxial semiconductor portion, and said second field effect transistor comprises a second capping semiconductor material portion in contact with a top surface of, and in epitaxial alignment with, said second epitaxial semiconductor portion, wherein said first and second capping semiconductor material portions have a same thickness.