Block Structure Profiling in Three Dimensional Memory

Abstract

Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes.

It is claimed: 
     
         1 . A method of characterizing a three-dimensional NAND memory die comprising:
 selecting a plurality of sample blocks from the three-dimensional NAND memory array;   writing sample data to a plurality of sample word lines of a plurality of physical levels of the sample blocks to obtain characterization information for the sample word lines; and   calculating a physical dimension of memory cells at each of the plurality of levels from the characterization information.   
     
     
         2 . The method of  claim 1  wherein the sample data consists of a predetermined test pattern for efficiently obtaining the characterization information. 
     
     
         3 . The method of  claim 2  wherein the test pattern assigns first logic states to memory cells on a drain side of a NAND string and assigns second logic states that are the inverse of the corresponding first logic states to corresponding memory cells on the source side of the NAND string. 
     
     
         4 . The method of  claim 1  wherein the physical dimension is a diameter of a vertical memory hole that extends through memory cells in each of the plurality of levels. 
     
     
         5 . The method of  claim 1  wherein the physical dimension is a thickness of a layer formed in a memory hole that extends through memory cells in each of the plurality of levels. 
     
     
         6 . The method of  claim 1  wherein the three-dimensional NAND memory die comprises a plurality of planes, and wherein selecting the plurality of sample blocks comprises selecting at least one sample block from each of the plurality of planes. 
     
     
         7 . The method of  claim 1  wherein the plurality of sample word lines of the plurality of physical levels includes at least one word line from each level in the three-dimensional NAND memory die. 
     
     
         8 . The method of  claim 1  wherein the plurality of sample word lines comprises all word lines of a sample block. 
     
     
         9 . The method of  claim 1  further comprising recording the physical dimension in the three-dimensional NAND memory die. 
     
     
         10 . The method of  claim 1  further comprising selecting operating parameters for memory cells at each of the plurality of levels based on the calculated physical dimension of memory cells at each of the plurality of levels. 
     
     
         11 . The method of  claim 10  wherein the operating parameters include programming voltage and/or programming time used during a write operation. 
     
     
         12 . The method of  claim 10  further comprising recording the selected operating parameters for each of the plurality of levels. 
     
     
         13 . The method of  claim 10  further comprising selecting parameter updating schemes for the selected operating parameters based on the calculated physical dimension of the memory cells at each of the plurality of levels. 
     
     
         14 . The method of  claim 13  wherein a first parameter updating scheme updates parameters associated with small memory hole diameter at a first rate and a second parameter updating scheme updates parameters associated with large memory hole diameter at a second rate that is different to the first rate. 
     
     
         15 . The method of  claim 14  wherein the first parameter updating scheme updates a wear level indicator associated with small memory hole diameter at the first rate and the second parameter updating scheme updates a wear level indicator associated with large memory hole diameter at a second rate that is slower than the first rate. 
     
     
         16 . A method of characterizing a three-dimensional NAND memory die comprising:
 selecting a plurality of sample blocks from the three-dimensional NAND memory array;   writing sample data to a plurality of sample word lines in a sample block, each physical level in a sample block containing at least one of the plurality of sample word lines, to obtain characterization information for the sample word lines; and   calculating a memory hole diameter at each physical level in the sample block from the characterization information.   
     
     
         17 . The method of  claim 16  wherein the write characterization information includes loop count information for programming the sample word lines. 
     
     
         18 . The method of  claim 16  wherein the write characterization information includes information obtained from verification when programming the sample word lines. 
     
     
         19 . The method of  claim 16  wherein the write characterization information includes maximum programming voltage information for programming the sample word lines. 
     
     
         20 . The method of  claim 16  further comprising calculating a wear rate for each level from the calculated memory hole diameter for the level. 
     
     
         21 . The method of  claim 20  wherein a wear rate for a particular level indicates the rate at which memory cells of the level approach a wear-out condition with increasing numbers of write-erase cycles. 
     
     
         22 . A three-dimensional NAND memory comprising:
 an array of memory cells arranged in a plurality of levels;   a plurality of memory hole structures extending vertically through the plurality of levels to connect memory cells of the plurality of levels in NAND strings;   a write circuit configured to write sample data to sample word lines at different levels of the plurality of levels; and   a characterization circuit configured to receive information regarding the writing of sample data to sample word lines from the write circuit, the characterization circuit determining one or more physical dimensions of a memory hole structure at the different levels from the information.   
     
     
         23 . The three-dimensional NAND memory of  claim 22  further comprising read circuits configured to read the sample data from the sample word lines at different levels of the plurality of levels and to send information regarding the reading of sample data to the characterization circuit. 
     
     
         24 . The three-dimensional NAND memory of  claim 23  wherein the information regarding the reading of sample data is used to determine the one or more physical dimensions. 
     
     
         25 . The three-dimensional NAND memory of  claim 22  wherein the one or more physical dimensions includes an outer dimension of the memory hole structure established by an inner dimension of a memory hole in which the memory hole structure is formed. 
     
     
         26 . The three-dimensional NAND memory of  claim 15  wherein the information regarding the writing of sample data to sample word lines includes at least one of: loop count information, verification information, and maximum programming voltage information for each of the sample word lines. 
     
     
         27 . A method of operating a three-dimensional NAND memory die comprising:
 testing memory cells at a plurality of levels in the three-dimensional NAND memory array to obtain characterization information for each of the plurality of levels;   calculating a physical dimension of memory cells at each of the plurality of levels from the characterization information;   calculating at least one initial value of an operating parameter for each of the plurality of levels, the initial value of the operating parameter for a level calculated from the physical dimension calculated for the level; and   calculating a rate of change of the operating parameter for each of the plurality of levels, the rate of change of the operating parameter for a level calculated from the physical dimension calculated for the level.   
     
     
         28 . The method of  claim 27  wherein the physical dimension is a diameter of a memory hole that extends through memory cells. 
     
     
         29 . The method of  claim 28  wherein a higher rate of change of the operating parameter is calculated for smaller memory hole diameter and a lower rate of change of the operating parameter is calculated for larger memory hole diameter. 
     
     
         30 . The method of  claim 27  further comprising, after a period of use, repeating testing of the memory cells at the plurality of levels in the three-dimensional NAND memory array to obtain post-use characterization information. 
     
     
         31 . The method of  claim 30  further comprising comparing the post-use characterization information with the characterization information and recalculating the physical dimension of memory cells at each of the plurality of levels from the post-use characterization information if a difference between the post use characterization information and the characterization information exceeds a threshold amount. 
     
     
         32 . The method of  claim 28  further comprising calculating an aggregated memory hole diameter for a block and calculating a wear rate for the block from the aggregated memory hole diameter. 
     
     
         33 . The method of  claim 32  further comprising calculating an effective age for the block from the number of write-erase cycles experienced by the block and the wear rate calculated for the block.