Electrically Conductive Pins For Microcircuit Tester

Abstract

The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface.

1 . (canceled) 
     
     
         2 . A method of lowering the resistance between a terminal on an integrated circuit and test fixture having
 an electrically conductive pin having a top surface engagable with the terminal,   the method comprising;   forming the top surface to include a longitudinal ridge along the surface, forming the ridge to have a sharp edge at its apex   
       whereby engagement of the ridge with the terminal will focus contact pressure over a small surface area and further cause ablation of oxides on the terminal. 
     
     
         3 .- 30 . (canceled) 
     
     
         31 . A test fixture ( 5 ), comprising:
 a membrane ( 10 ) extending laterally between a device under test ( 1 ) and a load board ( 3 ), the device under test ( 1 ) including a plurality of electrical terminals ( 2 ) arranged in a predetermined pattern, the load board ( 3 ) including a plurality of electrical contact pads ( 4 ) arranged in a predetermined pattern corresponding to that of the terminals ( 2 ), the membrane having a top side facing the terminals ( 2 ) of the device under test ( 1 ) and a bottom side facing the contact pads ( 4 ) of the load board ( 3 );   a plurality of electrical pin pairs ( 20 ,  30 ) supported by the membrane ( 10 ) in a predetermined pattern corresponding to that of the terminals ( 2 ), each pin pair in the plurality comprising:
 a top pin ( 20 ) extending through the top side of the membrane ( 10 ) and having a top pin mating surface ( 23 ); and 
 a bottom pin ( 30 ) extending through the bottom side of the membrane ( 10 ) and having a bottom pin mating surface ( 33 ); 
 wherein the top and bottom pin mating surfaces ( 23 ,  33 ) have complementary surface profiles; 
 wherein when the corresponding electrical terminal ( 2 ) is forced against the pin pair, the top and bottom pin mating surfaces ( 23 ,  33 ) slide along each other along a virtual interface surface ( 70 ); and 
 wherein the virtual interface surface ( 70 ) is inclined with respect to a surface normal of the membrane ( 10 ). 
   
     
     
         32 . The test fixture ( 5 ) of  claim 31 , wherein the membrane ( 10 ) includes a plurality of membrane layers. 
     
     
         33 . The test fixture ( 5 ) of  claim 32 , wherein at least two of the membrane layers in the plurality have different mechanical properties. 
     
     
         34 . The test fixture ( 5 ) of  claim 31 , wherein the membrane ( 10 ) is monolithic. 
     
     
         35 .- 38 . (canceled) 
     
     
         39 . An electrical contact pin for engagement with an a device under test having electrical contact array on an integrated circuit or similar device having a plurality of adjacent contacts, the pin being having a top surface, said top surface comprising:
 a projecting land extending generally orthogonally upwardly from said top surface, said projection including a generally narrow longitudinal contact area which is engagable with a contact of the integrated circuit, said contact area being substantially narrower than that of the top surface and the contact area having a surface area substantially less than that of the top surface.   
     
     
         40 . The pin of  claim 39  wherein said narrow contact area comprises a peak formed of two converging sidewalls rising from the top surface. 
     
     
         41 . The pin of  claim 40  wherein the sidewall are generally hemispherical. 
     
     
         42 . The pin of  claim 40  wherein the sidewalls are generally convex. 
     
     
         43 . The pin of  claim 40  wherein said sidewalls are first sidewalls generally hemispherical and further includes a secondary set of sidewall rising from the first sidewalls and converging to an apex. 
     
     
         44 . The pin of  claim 39  wherein said narrow contact area is flat and includes a pair of parallel sidewalls rising from the top surface, thereby creating a land. 
     
     
         45 . The pin of  claim 44  wherein said narrow contact surface area is an apex rising from said parallel sidewalls. 
     
     
         46 . The pin of  claim 39  wherein said projecting land include a plurality of adjacent spaced apart lands each having an apex for contacting a single integrated circuit contact at a plurality of point on said contact. 
     
     
         47 . The pin of  claim 46  wherein said plurality of lands are parallel to each other. 
     
     
         48 . The pin of  claim 46  wherein at least two of the lands are non-parallel to each other. 
     
     
         49 . The pin of  claim 39  wherein said longitudinal contact area is not smooth. 
     
     
         50 . The pin of  claim 39  wherein said longitudinal contact area includes notches therealong. 
     
     
         51 . The pin of  claim 39  wherein said longitudinal contact area is skewed along the top surface of the pin. 
     
     
         52 . (canceled) 
     
     
         53 . The method of  claim 2  further including the steps of slideably engaging the pin and terminal then they are brought together and skewing the longitudinal ridge placement on the pin to increase drag between the ridge and the terminal when brought together.