Design and integration of finfet device

Abstract

An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a substrate comprising a semiconductor material;   isolation oxide disposed over the substrate;   a first fin field effect transistor (finFET), comprising:
 a first fin of semiconductor material disposed on the substrate, the isolation oxide being disposed adjacent to the first fin, the first fin having a first exposed fin height; and 
 a first gate disposed over the first fin and extending down sidewalls of the first fin; and 
   a second finFET, comprising:
 a second fin of semiconductor material disposed on the substrate, the isolation oxide being disposed adjacent to the second fin, the second fin having a second exposed fin height, such that the first exposed fin height and the second exposed fin height differ by at least 25 percent; and 
 a second gate disposed over the second fin and extending down sidewalls of the second fin. 
   
     
     
         2 . The integrated circuit of  claim 1 , wherein:
 a thickness of the isolation oxide adjacent to the first fin and the second fin is substantially uniform; and   a fin height of the first finFET is less than a fin height of the second finFET, the fin height of a fin being a height of a top of the fin above the substrate adjacent to the fin, so that the first exposed fin height is at least 25 percent less than second exposed fin height.   
     
     
         3 . The integrated circuit of  claim 2 , wherein:
 the first finFET is a passgate finFET in a static random access memory (SRAM) cell; and   the second finFET is a driver finFET in the SRAM cell.   
     
     
         4 . The integrated circuit of  claim 1 , wherein:
 a fin height of the first finFET is substantially equal to a fin height of the second finFET; and   a thickness of the isolation oxide adjacent to the first fin is less than a thickness of the isolation oxide adjacent to the second fin, so that the first exposed fin height is at least 25 percent more than second exposed fin height.   
     
     
         5 . The integrated circuit of  claim 4 , wherein:
 the first finFET is a driver finFET in an SRAM cell; and   the second finFET is a passgate finFET in the SRAM cell.   
     
     
         6 . The integrated circuit of  claim 1 , wherein a width of the first fin and a width of the second fin are substantially equal. 
     
     
         7 . The integrated circuit of  claim 1 , wherein pitch distances between centers of the first fin and fins adjacent to the first fin, and pitch distances between centers of the second fin and fins adjacent to the second fin, are all substantially equal. 
     
     
         8 . The integrated circuit of  claim 1 , wherein a width of the first gate and a width of the second gate are substantially equal. 
     
     
         9 . The integrated circuit of  claim 1 , wherein pitch distances between centers of the first gate and gates adjacent to the first gate, and pitch distances between centers of the second gate and gates adjacent to the second gate, are all substantially equal. 
     
     
         10 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising a semiconductor material;   forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;   forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;   forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the first fin and covers the second fin;   removing the semiconductor material from a top of the first fin without removing the semiconductor material from a top of the second fin, so that an exposed fin height of the first fin is at least 25 percent less than an exposed fin height of the second fin; and   forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.   
     
     
         11 . The method of  claim 10 , wherein:
 the first finFET is a passgate finFET in an SRAM cell; and   the second finFET is a driver finFET in the SRAM cell.   
     
     
         12 . The method of  claim 10 , wherein the first fin and the second fin are formed with substantially equal widths. 
     
     
         13 . The method of  claim 10 , wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances. 
     
     
         14 . The method of  claim 10 , wherein the first gate and the second gate are formed with substantially equal widths. 
     
     
         15 . The method of  claim 10 , wherein the first gate and gates adjacent to the first gate, and the second gate and gates adjacent to the second gate, are formed on substantially equal pitch distances. 
     
     
         16 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising a semiconductor material;   forming a first fin of semiconductor material of a first finFET and a second fin of semiconductor material of a second finFET on the substrate, so that a fin height of the first fin is substantially equal to a fin height of the second fin;   forming isolation oxide over the substrate adjacent to the first fin and the second fin, so that the first fin and the second fin extend above the isolation oxide;   forming an etch mask over the first fin, the second fin and the isolation oxide which exposes the isolation oxide adjacent to the first fin and covers the isolation oxide adjacent to the second fin;   removing a portion of the isolation oxide from areas exposed by the etch mask, so that an exposed fin height of the first fin is at least 25 percent greater than an exposed fin height of the second fin; and   forming a first gate of the first finFET over the first fin so as to extend down sidewalls of the first fin substantially to the isolation oxide and forming a second gate of the second finFET over the second fin so as to extend down sidewalls of the second fin substantially to the isolation oxide.   
     
     
         17 . The method of  claim 16 , wherein:
 the first finFET is a driver finFET in an SRAM cell; and   the second finFET is a passgate finFET in the SRAM cell.   
     
     
         18 . The method of  claim 16 , wherein the first fin and the second fin are formed with substantially equal widths. 
     
     
         19 . The method of  claim 16 , wherein the first fin and fins adjacent to the first fin, and the second fin and fins adjacent to the second fin, are formed on substantially equal pitch distances. 
     
     
         20 . The method of  claim 16 , wherein the first gate and the second gate are formed with substantially equal widths.