Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces

Abstract

The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.

1 . A method of forming an integrated circuit, comprising:
 providing a surface comprising a first region and a second region, the first region formed of a different material than the second region;   forming a seeding material in contact with and across the first and second regions; and   forming a metal comprising tungsten on the seeding material.   
     
     
         2 . The method of  claim 1 , wherein forming the seeding material comprises forming an amorphous material. 
     
     
         3 . The method of  claim 1 , wherein at least one of the first region and the second region comprises a dielectric. 
     
     
         4 . The method of  claim 1 , wherein the metal comprises alpha-phase tungsten. 
     
     
         5 . The method of  claim 1 , wherein the metal consists essentially of alpha-phase tungsten. 
     
     
         6 . The method of  claim 1  wherein forming the seeing material comprises depositing the seeding material using one of chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). 
     
     
         7 . The method of  claim 1 , wherein forming the metal comprises depositing tungsten using physical vapor deposition. 
     
     
         8 . A method of forming a memory device, comprising:
 providing a memory cell stack adjacent an insulating material, the memory cell stack comprising an electrode material;   forming a seeding material in contact with and across the electrode material and the insulating material;   forming a metal comprising tungsten on the seeding material; and   patterning the metal to form a conductive access line.   
     
     
         9 . The method of  claim 8 , wherein providing the memory cell stack comprises providing the electrode material over a chalcogenide element. 
     
     
         10 . The method of  claim 8 , wherein forming the metal comprises forming alpha-phase tungsten. 
     
     
         11 . The method of  claim 8 , wherein forming the seeding material comprises depositing amorphous silicon. 
     
     
         12 . The method of  claim 8 , wherein the insulating material comprises silicon oxide. 
     
     
         13 . The method of  claim 8 , wherein forming the metal comprises depositing using physical vapor deposition. 
     
     
         14 . The method of  claim 8 , wherein forming the metal deposits a tungsten layer having a thickness not exceeding about 10 nm. 
     
     
         15 . The method of  claim 8 , wherein providing the memory cell stack comprises:
 etching a carbon material over a chalcogenide material to form a carbon electrode line;   filling a gap adjacent the carbon electrode line with the insulating material; and   planarizing to form a substantially planarized surface comprising the electrode carbon line adjacent the insulating material.   
     
     
         16 . The method of  claim 15 , wherein the metal over the carbon electrode lines has a first average grain size and the metal over the insulating material has a second average grain size, wherein the first and second average grain sizes are approximately similar. 
     
     
         17 . The method of  claim 15 , wherein the carbon electrode line extends in a first direction, and patterning the metal comprises etching the metal and the seeding material to form the conductive access line extending in a second direction crossing the first direction. 
     
     
         18 . The method of  claim 15 , wherein patterning the metal further comprises:
 etching the carbon electrode line to form a carbon electrode electrically isolated in both first and second directions.   
     
     
         19 . A memory cell, comprising:
 a first conductive line extending in a first direction;   a second conductive line comprising tungsten disposed above a seeding line formed of a seeding material, the second conductive line extending in a second direction crossing the first conductive line; and   a chalcogenide element interposed between the first and second conductive lines,   wherein the seeding line is interposed between the second conductive line and the chalcogenide element, the seeding line contacting the second conductive line.   
     
     
         20 . The memory cell of  claim 19 , wherein the seeding material comprises an amorphous material. 
     
     
         21 . The memory cell of  claim 20 , wherein the seeding material comprises amorphous silicon. 
     
     
         22 . The memory cell of  claim 19 , further comprising a carbon electrode interposing the chalcogenide element and the seeding line. 
     
     
         23 . The memory cell of  claim 19 , wherein the second conductive line comprises alpha-phase tungsten and is substantially free of beta-phase tungsten. 
     
     
         24 . The memory cell of  claim 19 , wherein the seeding line has a thickness between about 1 nm and about 3 nm. 
     
     
         25 . The memory cell of  claim 19 , wherein the second conductive line has a thickness not exceeding about 10 nm. 
     
     
         26 . The memory cell of  claim 19 , wherein the first conductive line comprises tungsten and is disposed above a first seeding line formed of an amorphous material.