Patterned structure of semiconductor device

Abstract

A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.

What is claimed is: 
     
         1 . A patterned structure of a semiconductor device, comprising:
 a substrate;   at least a first patterned structure disposed on the substrate, wherein the first patterned structure is a single-layered structure; and   at least a second patterned structure disposed on the substrate, wherein the second patterned structure is a multi-layered structure, and a width of the second patterned structure is greater than a width of the first patterned structure.   
     
     
         2 . The patterned structure of  claim 1 , wherein the first patterned structure and the second patterned structure respectively consist of spacers. 
     
     
         3 . The patterned structure of  claim 1 , wherein the first patterned structure has a sub-lithographic feature. 
     
     
         4 . The patterned structure of  claim 1 , wherein the first patterned structure is parallel to the second patterned structure. 
     
     
         5 . The patterned structure of  claim 1 , further comprising a third patterned structure, wherein the third patterned structure is a multi-layered structure, and a width of the third patterned structure is greater than the width of the second patterned structure. 
     
     
         6 . The patterned structure of  claim 1 , wherein the semiconductor device is a static random access memory (SRAM) comprising a plurality of transistors.