Method and system for a gallium nitride vertical transistor

Abstract

A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

What is claimed is: 
     
         1 . A method of fabricating a vertical JFET, the method comprising:
 providing a III-nitride epitaxial structure including:
 a III-nitride substrate; and 
 a plurality of epitaxial layers coupled to the III-nitride substrate; 
   removing a portion of the plurality of epitaxial layers to form a set of recesses extending a predetermined distance into the plurality of epitaxial layers, wherein the set of recesses are disposed between remaining portions of the plurality of epitaxial layers;   regrowing a plurality of regrown epitaxial layers coupled to at least a portion of one of the plurality of epitaxial layers and the remaining portions of the plurality of epitaxial layers, wherein one of the plurality of regrown epitaxial layers is electrically coupled to one of the plurality of epitaxial layers;   removing a portion of the plurality of regrown epitaxial layers to expose a portion of the one of the plurality of epitaxial layers;   forming a source contact electrically coupled to the one of the plurality of epitaxial layers;   forming a gate contact electrically coupled to another of the plurality of epitaxial layers; and   forming a drain contact electrically coupled to the III-nitride substrate.   
     
     
         2 . The method of  claim 1  wherein regrowing the plurality of regrown epitaxial layers comprises:
 regrowing a first epitaxial layer of a first conductivity type; and 
 regrowing a second epitaxial layer of a second conductivity type different from the first conductivity type. 
 
     
     
         3 . The method of  claim 1  wherein at least one of the plurality of regrown epitaxial layers is a conformal layer. 
     
     
         4 . The method of  claim 1  wherein the one of the plurality of epitaxial layers comprises a first part of the source channel and one of the regrown epitaxial layers comprises a second part of the source channel. 
     
     
         5 . The method of  claim 4  wherein and the another of the plurality of epitaxial layers comprises a gate region of the vertical JFET. 
     
     
         6 . The method of  claim 5  wherein the first part of the source channel is electrically shorted to the second part of the second channel and the source channel is characterized by a doping opposite to the gate region. 
     
     
         7 . The method of  claim 1  wherein the plurality of regrown epitaxial layers are characterized by a thickness equal to the predetermined distance. 
     
     
         8 . The method of  claim 1  wherein one of the plurality of epitaxial layers comprises at least one of n-type doped GaN or an AlGaN/GaN material forming a two dimensional electric gas (2DEG). 
     
     
         9 . The method of  claim 8  wherein the one of the plurality of epitaxial layers comprises a first part of a source channel.