Finfet Drive Strength Modification

Abstract

A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

1 . A device comprising:
 a first transistor formed on a substrate, wherein the first transistor includes an active region; and   a second transistor formed on the substrate, wherein the first and second transistors share the active region, and   wherein the first transistor is without any low density doped (LDD) extension regions in the substrate and wherein the second transistor is associated with a first LDD extension region formed in the substrate such that a drive strength of the second transistor is greater relative to a drive strength of the first transistor.   
     
     
         2 . The device of  claim 1 , further comprising a first high density doped (HDD) region associated with the second transistor and wherein the first LDD extension region extends from the first HDD region. 
     
     
         3 . The device of  claim 2 , further comprising a second LDD extension region associated with the second transistor. 
     
     
         4 . The device of  claim 3 , further comprising a second HDD region associated with the second transistor and wherein the second LLD extension region extends from the second HDD region. 
     
     
         5 . The device of  claim 1 , wherein the first transistor is a pass gate transistor of a SRAM cell. 
     
     
         6 . The device of  claim 5 , wherein the second transistor is a pull down transistor of the SRAM cell. 
     
     
         7 . The device of  claim 1 , further comprising a third transistor formed on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor. 
     
     
         8 . A device comprising:
 a first transistor formed on a substrate, wherein the first transistor includes an active region;   a second transistor formed on the substrate, wherein the first transistor and the second transistor share the active region; and   a first high density doped (HDD) region and a second high density doped (HDD) region formed in the substrate, wherein the first transistor is without a first low density doped (LDD) extension region in the substrate extending from the first HDD region or a second LDD extension region in the substrate extending from the second HDD region toward the gate region such that such that a drive strength of the first transistor is reduced relative to a drive strength of the second transistor associated with at least one of the first and second LDD extension regions.   
     
     
         9 . The device of  claim 8 , wherein the first transistor is without the first and second LDD extension regions. 
     
     
         10 . The device of  claim 8 , wherein the first transistor is without any LDD extension regions. 
     
     
         11 . The device of  claim 8 , wherein the second transistor is associated with both the first and second LDD extension regions. 
     
     
         12 . The device of  claim 8 , wherein the device a complementary metal oxide semiconductor (CMOS) device. 
     
     
         13 . The device of  claim 8 , wherein the first transistor is a pass gate transistor of a SRAM cell, and
 wherein the second transistor is a pull down transistor of the SRAM cell.   
     
     
         14 . The device of  claim 8 , further comprising a third transistor formed on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor. 
     
     
         15 . A method comprising:
 forming a high density doped (HDD) region in a semiconductor substrate;   forming a low density doped (LDD) extension region in the semiconductor substrate, wherein the LDD extension region interfaces with the HDD region;   forming a first transistor on the semiconductor substrate, wherein the first transistor includes an active region, and wherein the first transistor is without the LDD extension region in the semiconductor; and   forming a second transistor on the semiconductor substrate, wherein the first and second transistors share the active region, and wherein the second transistor is associated with the LDD extension region such that a drive strength of the second transistor is greater relative to a drive strength of the first transistor.   
     
     
         16 . The method of claim  37 , wherein the second transistor is not associated with any other LDD extension region. 
     
     
         17 . The method of  claim 15 , further comprising forming another HDD region in the semiconductor substrate, and
 forming another LDD extension region in the semiconductor substrate extending from the another HDD region toward the gate region, and   wherein the second transistor is associated with the another LDD extension region.   
     
     
         18 . The method of  claim 15 , wherein the first transistor is a pass gate transistor of a SRAM cell, and
 wherein the second transistor is a pull down transistor of the SRAM cell.   
     
     
         19 . The method of  claim 15 , wherein the first transistor is without any LDD extension regions. 
     
     
         20 . The method of  claim 15 , further comprising forming a third transistor on the substrate, wherein a drive strength of the third transistor is greater relative to the drive strength of the second transistor.