Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

Abstract

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

1 . A semiconductor die assembly, comprising:
 a first logic die;   a second logic die; and   a stack of memory dies disposed between the first and second logic dies.   
     
     
         2 . The die assembly of  claim 1  wherein:
 the first logic die includes a memory controller; and 
 the second logic die includes a communication component. 
 
     
     
         3 . The die assembly of  claim 2  wherein the communication component includes a serial/deserializer circuit. 
     
     
         4 . The die assembly of  claim 1 , further comprising a thermally conductive casing defining an enclosure, wherein the stack of memory dies are disposed within the enclosure. 
     
     
         5 . The die assembly of  claim 4  wherein the second logic die is disposed between the thermally conductive casing and the stack of memory dies, and wherein the second logic die is electrically coupled to the first logic die via the stack of memory dies. 
     
     
         6 . The die assembly of  claim 5  wherein the second logic die includes a semiconductor substrate, and wherein the semiconductor substrate does not include any through-die interconnects extending through the semiconductor substrate. 
     
     
         7 . The die assembly of  claim 1  wherein:
 the first logic die has a first thickness; and 
 the second logic die has a second thickness that is less than the first thickness. 
 
     
     
         8 . The die assembly of  claim 7  wherein:
 the first thickness is in the range of about 50 μm to about 200 μm; and 
 the second thickness is in the range of about 300 μm to about 1000 μm. 
 
     
     
         9 . The die assembly of  claim 1 , further comprising a plurality of through-stack interconnects extending through the stack of memory dies and electrically coupling the first logic die with the second logic die. 
     
     
         10 . The die assembly of  claim 1 , further comprising a plurality of through-stack interconnects extending through the stack of memory dies and electrically coupling the second logic die with individual memory dies of the stack of memory dies. 
     
     
         11 . A semiconductor die assembly, comprising:
 a thermally conductive casing;   a first semiconductor die attached to a first portion of the thermally conductive casing;   a second semiconductor die attached to a second portion of the thermally conductive casing separate from the first portion;   a stack of third semiconductor dies at least partially enclosed within the thermally conductive casing; and   a plurality of through-stack interconnects extending through the stack of third semiconductor dies,   wherein—
 the stack of third semiconductor dies is disposed between the first and second semiconductor dies, and 
 at least a portion of the through-stack interconnects electrically couple the first semiconductor die with the second semiconductor die. 
   
     
     
         12 . The die assembly of  claim 11  wherein another portion of the through-stack interconnects is functionally isolated from the first semiconductor die. 
     
     
         13 . The die assembly of  claim 11  wherein the portion of the through-stack interconnects provides dedicated circuit paths between the first and second semiconductor dies. 
     
     
         14 . The die assembly of  claim 11  wherein:
 the first semiconductor die includes a controller component; and 
 the second semiconductor die includes a communication component operably coupled to the controller component via the portion of the through-stack interconnects. 
 
     
     
         15 . The die assembly of  claim 11 , further comprising a package substrate carrying the first semiconductor die, wherein:
 the package substrate includes a plurality of package contacts; and   the first semiconductor die includes a serializer/deserializer circuit coupled between the package contacts and the portion of the through-stack interconnects.   
     
     
         16 . A semiconductor die assembly, comprising:
 a first logic die configured to receive a serial data stream and to deserialize the serial data stream into parallel data streams;   a stack of memory dies; and   a second logic die carried by the stack of memory dies, wherein the second logic die is configured to receive the parallel data streams via the stack of memory dies.   
     
     
         17 . The die assembly of  claim 16  wherein the first logic die includes a memory controller configured to receive the parallel data streams via the stack of memory dies. 
     
     
         18 . The die assembly of  claim 16 , further comprising a package substrate, wherein the first logic die is configured to receive the serial data stream via the package substrate. 
     
     
         19 . The die assembly of  claim 18  wherein the first logic die and the stack of memory dies are attached to the package substrate at different locations. 
     
     
         20 . The die assembly of  claim 18  wherein the first logic die is disposed between the package substrate and the of stack of memory dies. 
     
     
         21 - 34 . (canceled) 
     
     
         35 . A semiconductor system, comprising:
 a hybrid memory cube (HMC), including—
 a first logic die, 
 a second logic die, 
 a stack of memory dies disposed between the first logic die and the second logic die, and 
 a thermally conductive casing attached to the second logic die and enclosing the stack of memory dies within an enclosure; and 
   a driver electrically coupled to the first logic die.