Non-volatile register and non-volatile shift register

Abstract

Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

What is claimed is: 
     
         1 . An non-volatile register for initial loading and outputting N-bit data in parallel upon power-on, comprising:
 N non-volatile register cells arranged in a row, each non-volatile register cell comprising:   a static memory element comprising two inverters, a first output node and a second output node;   a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node; and   a reset transistor coupled to the second output node for resetting the second output node to a predetermined voltage;   wherein a gate of each reset transistor is connected with each other to form a reset line;   wherein the control gate of each NVM element is connected with each other to form a first voltage line and the second source/drain electrode of each NVM element is connected with each other to form a second voltage line;   wherein the non-volatile register cells output the N-bit data in parallel at their second output nodes; and   wherein the predetermined voltage and a threshold voltage state of the NVM element determine a logic state of the second output node upon power-up for each non-volatile register cell.   
     
     
         2 . The non-volatile register according to  claim 1 , wherein when the reset transistor is N-type, the reset transistor is coupled between the second output node and a ground node carrying a ground voltage for each non-volatile register cell, otherwise the reset transistor is coupled between the second output node and an operating node carrying an operating voltage for each non-volatile register cell. 
     
     
         3 . The non-volatile register according to  claim 2 , wherein the second output node is reset to the predetermined voltage for each non-volatile register cell when a gate voltage is applied to the reset line. 
     
     
         4 . The non-volatile register according to  claim 3 , wherein when the reset transistor is N-type, the gate voltage is the operating voltage and the predetermined voltage is the ground voltage for each non-volatile register cell, and wherein when the reset transistor is P-type, the gate voltage is the ground voltage and the predetermined voltage is the operating voltage for each non-volatile register cell. 
     
     
         5 . The non-volatile register according to  claim 1 , wherein when the NVM element is N-type, a control gate voltage is applied to the first voltage line and a ground voltage is applied to the second voltage line to load an non-volatile value from the NVM element into the static memory element for each non-volatile register cell, and wherein the control gate voltage is between a programmed threshold voltage and an erased threshold voltage of the NVM element. 
     
     
         6 . The non-volatile register according to  claim 1 , wherein when the NVM element is P-type, an operating voltage is applied to the first voltage line, the second voltage line and a well electrode of the NVM element to load an non-volatile value from the NVM element into the static memory element for each non-volatile register cell. 
     
     
         7 . The non-volatile register according to  claim 1 , wherein after the second output node is reset and then an non-volatile value is loaded from the NVM element into the static memory element, the second output node has the ground voltage if the NVM element is in a programmed threshold voltage state for each non-volatile register cell and the second output node has the operating voltage if the NVM element is in an erased threshold voltage state for each non-volatile register cell. 
     
     
         8 . The non-volatile register according to  claim 1 , wherein the static memory element comprises a latch for each non-volatile register cell. 
     
     
         9 . An operating method of a non-volatile register for initial loading and outputting N-bit data in parallel upon power-on, the non-volatile register comprising N non-volatile register cells arranged in a row, each non-volatile register cell comprising a static memory element, a non-volatile memory (NVM) element and a reset transistor, the static memory element having comprising two inverters, a first output node and a second output node, a first source/drain electrode of the NVM element being coupled to the first output node, the reset transistor coupled to the second output node, wherein a gate of each reset transistor is connected with each other to form a reset line, wherein a control gate of each NVM element is connected with each other to form a first voltage line and a second source/drain electrode of each NVM element is connected with each other to form a second voltage line, the operating method comprising the sequential steps of:
 resetting each second output node to a predetermined voltage by its corresponding reset transistor; 
 when the NVM element is N-type, loading an non-volatile value from the NVM element into the static memory element by applying a control gate voltage to the first voltage line and applying a ground voltage to the second voltage line for each non-volatile register cell; 
 when the NVM element is P-type, loading the non-volatile value from the NVM element into the static memory element by applying an operating voltage to the first voltage line, the second voltage line and a well electrode of the NVM element for each non-volatile register cell; and 
 outputting the N-bit data in parallel at the second output nodes of the N non-volatile register cells; 
 wherein the control gate voltage is between an erased threshold voltage and a programmed threshold voltage of the NVM element; and 
 wherein the predetermined voltage and a threshold voltage state of the NVM element determine a logic state of the second output node upon power-up for each non-volatile register cell. 
 
     
     
         10 . The method according to  claim 9 , wherein the step of resetting comprises:
 when the reset transistor is N-type, applying the operating voltage to a gate of the reset transistor to reset the second output node to the ground voltage for each non-volatile register cell; and   when the reset transistor is P-type, applying the ground voltage to the gate of the reset transistor to reset the second output node to the operating voltage for each non-volatile register cell.   
     
     
         11 . The method according to  claim 9 , wherein each NVM element is N-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned off for each non-volatile register cell, otherwise the NVM element is turned on during the step of loading the non-volatile value from the NVM element into the static memory element for each non-volatile register cell. 
     
     
         12 . The method according to  claim 9 , wherein each NVM element is P-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned on, otherwise the NVM element is turned off during the step of loading the non-volatile value from the NVM element into the static memory element. 
     
     
         13 . The method according to  claim 9 , further comprising:
 when the NVM element is in a programmed threshold voltage state, causing the second output node to have the ground voltage for each non-volatile register cell, otherwise causing the second output node to have the operating voltage after the step of loading the non-volatile value from the NVM element into the static memory element.