Shallow trench isolation

Abstract

A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

1 .- 8 . (canceled) 
     
     
         9 . A method of forming a semiconductor structure, comprising:
 forming a shallow trench isolation (STI) cavity on the semiconductor substrate;   depositing a first fill oxide in the shallow trench isolation cavity;   recessing the first fill oxide to a depth below the semiconductor substrate;   depositing a high Young's modulus liner on along a first sidewall of the STI cavity to the depth below the semiconductor substrate, along a second sidewall of the STI cavity to the depth below the semiconductor substrate, and along the top portion of the recessed first fill oxide; and   depositing a second fill oxide in the shallow trench isolation cavity.   
     
     
         10 . The method of  claim 9 , further comprising planarizing the second fill oxide. 
     
     
         11 . The method of  claim 10 , wherein planarizing the second fill oxide is performed with a chemical mechanical polish. 
     
     
         12 . The method of  claim 9 , wherein depositing a high Young's modulus liner comprises depositing a liner having a thickness ranging from about 5 nanometers to about 10 nanometers. 
     
     
         13 . The method of  claim 9 , wherein recessing the first fill oxide is performed with a reactive ion etch process. 
     
     
         14 . The method of  claim 9 , wherein recessing the first fill oxide is performed with a wet etch process. 
     
     
         15 . The method of  claim 9 , wherein the semiconductor structure comprises a field effect transistor comprising an embedded stressor source-drain region, and wherein recessing the first fill oxide comprises recessing the first fill oxide to a level below the embedded stressor source-drain region. 
     
     
         16 . The method of  claim 15 , wherein recessing the first fill oxide comprises recessing to a depth ranging from about 20 nanometers to about 30 nanometers. 
     
     
         17 . A method of forming a semiconductor structure, comprising:
 forming a first field effect transistor and a second field effect transistor on a semiconductor substrate;   forming a shallow trench isolation (STI) cavity between the first field effect transistor and the second field effect transistor;   depositing a first fill oxide in the shallow trench isolation cavity;   recessing the first fill oxide to a depth below the semiconductor substrate;   depositing a high Young's modulus liner via atomic layer deposition on along a first sidewall of the STI cavity to the depth below the semiconductor substrate, along a second sidewall of the STI cavity to the depth below the semiconductor substrate, and along the top portion of the recessed first fill oxide; and   depositing a second fill oxide in the shallow trench isolation cavity.   
     
     
         18 . The method of  claim 17 , wherein depositing a high Young's modulus liner comprises depositing hafnium oxide. 
     
     
         19 . The method of  claim 17 , wherein depositing a high Young's modulus liner comprises depositing aluminum oxide. 
     
     
         20 . The method of  claim 17 , wherein depositing a high Young's modulus liner comprises depositing silicon nitride. 
     
     
         21 . The method of  claim 9 , wherein the high Young's modulus liner has a Young's modulus ranging from about 220 GPa to about 400 GPa. 
     
     
         22 . The method of  claim 17 , wherein the high Young's modulus liner has a thickness ranging from about 5 nanometers to about 10 nanometers. 
     
     
         23 . The method of  claim 17 , wherein the high Young's modulus liner has a Young's modulus ranging from about 220 GPa to about 400 GPa. 
     
     
         24 . A semiconductor structure comprising:
 a semiconductor substrate;   a shallow trench isolation (STI) cavity in the semiconductor substrate, wherein the STI cavity contains a first fill oxide to a depth below the semiconductor substrate; a high Young's modulus liner along a first sidewall of the STI cavity to the depth below the semiconductor substrate, along a second sidewall of the STI cavity to the depth below the semiconductor substrate, and along the top portion of the first fill oxide; and a second fill oxide above the first fill oxide and the high Young's modulus liner.   
     
     
         25 . The semiconductor structure of  claim 24 , wherein the high Young's modulus liner comprises hafnium oxide, aluminum oxide, or silicon nitride. 
     
     
         26 . The semiconductor structure of  claim 24 , wherein the high Young's modulus liner has a thickness ranging from about 5 nanometers to about 10 nanometers. 
     
     
         27 . The semiconductor structure of  claim 24 , wherein the high Young's modulus liner has a Young's modulus ranging from about 220 GPa to about 400 GPa. 
     
     
         28 . The semiconductor structure of  claim 24 , wherein the second fill oxide is substantially flush with the top of the semiconductor substrate.