Optimized layer for semiconductor

Abstract

Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.

What is claimed is: 
     
         1 . A semiconductor component, comprising:
 a substrate layer cut from an initial wafer and bonded to an acceptor wafer, one or more doping properties of the substrate layer tuned based on a type of the semiconductor component; and   a second layer formed on a surface of the substrate layer, the second layer having a greater thickness than the substrate layer and a lesser doping density than the substrate layer.   
     
     
         2 . The semiconductor component of  claim 1 , further comprising a metallic layer formed on another surface of the substrate layer. 
     
     
         3 . The semiconductor component of  claim 1 , wherein at least one of the substrate layer and the second layer comprises silicon carbide (SiC). 
     
     
         4 . The semiconductor component of  claim 3 , wherein the substrate layer comprises a highly doped p-type substrate. 
     
     
         5 . The semiconductor component of  claim 1 , wherein the substrate layer is substantially homogeneously doped using epitaxy or implantation at a doping density greater than or equal to 10 20  cm −3 . 
     
     
         6 . The semiconductor component of  claim 1 , wherein the substrate layer is comprised of a first portion having an n-type doping and an adjacent second portion having a p-type doping. 
     
     
         7 . The semiconductor component of  claim 1 , wherein the substrate layer is comprised of a plurality of laterally oriented portions alternately having an n-type doping and a p-type doping. 
     
     
         8 . The semiconductor component of  claim 1 , wherein the substrate layer is formed on the initial wafer and is transferred to the acceptor wafer prior to forming the second layer. 
     
     
         9 . The semiconductor component of  claim 1 , wherein the second layer is epitaxially formed on the surface of the substrate layer. 
     
     
         10 . A silicon carbide (SiC) semiconductor device, comprising:
 a poly-silicon carbide acceptor wafer;   a highly doped, low impedance SiC substrate layer having a first thickness and having a tuned doping characteristic, bonded at a first surface of the substrate layer to a surface of the acceptor wafer; and   a lightly doped SiC component layer epitaxially formed on another surface of the substrate layer and arranged to be doped to form a desired component, the acceptor wafer being removed from the substrate layer as part of forming the desired component.   
     
     
         11 . The SiC semiconductor device of  claim 10 , further comprising an insulating layer between the substrate layer and the acceptor wafer, the insulating layer arranged to be removed from the substrate layer as part of forming the desired component. 
     
     
         12 . The SiC semiconductor device of  claim 10 , the substrate layer further comprising one or more at least partially filled trenches. 
     
     
         13 . The SiC semiconductor device of  claim 12 , wherein the one or more trenches are arranged with variations in spacing and/or thickness. 
     
     
         14 . The SiC semiconductor device of  claim 12 , wherein one or more of the trenches are filled with a doping that is an opposite doping type as the substrate layer. 
     
     
         15 . The SiC semiconductor device of  claim 12 , wherein sidewalls of the one or more trenches are implanted with a doping that is an opposite doping type as the substrate layer. 
     
     
         16 . A method, comprising:
 doping a semiconductor wafer to a desired extent to form a substrate layer;   transferring the substrate layer of the semiconductor wafer to an acceptor wafer;   forming a component layer on a surface of the substrate layer;   detaching the acceptor wafer from the substrate layer.   
     
     
         17 . The method of  claim 16 , further comprising doping the semiconductor wafer substantially uniformly over an area of the semiconductor wafer or doping the semiconductor wafer using a masked implantation or a trench fill epitaxy process, to form the substrate layer. 
     
     
         18 . The method of  claim 16 , further comprising doping the semiconductor wafer in alternating portions of n-type and p-type doping, to form the substrate layer. 
     
     
         19 . The method of  claim 16 , further comprising implanting the semiconductor wafer with hydrogen ions to a desired depth and cutting the substrate layer from the semiconductor wafer at the desired depth to determine a thickness of the substrate layer. 
     
     
         20 . The method of  claim 16 , further comprising bonding the substrate layer to the acceptor wafer using an oxidic bonding process. 
     
     
         21 . The method of  claim 16 , further comprising forming an insulating layer on a surface of the substrate layer prior to transferring the substrate layer to the acceptor wafer. 
     
     
         22 . The method of  claim 21 , further comprising removing the insulating layer in addition to the acceptor wafer from the substrate layer and doping an exposed surface of the substrate layer. 
     
     
         23 . The method of  claim 16 , further comprising forming the component layer on the surface of the substrate layer using a lighter doping density than a doping density of the substrate layer. 
     
     
         24 . The method of  claim 16 , further comprising applying and annealing a metallization layer to a surface of the substrate layer that is exposed by detaching the acceptor wafer from the substrate layer. 
     
     
         25 . The method of  claim 16 , further comprising coupling a stabilizing layer to an exposed surface of the component layer during processing and removing the stabilizing layer after processing.