Semiconductor device attached to an exposed pad

Abstract

The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

What is claimed is: 
     
         1 . A packaged semiconductor device comprising:
 a die having an active surface and a backside surface opposite the active surface; and   an exposed pad of a lead frame, wherein
 a first surface of the exposed pad is joined to die attach material, 
 the die attach material is further joined to the backside surface of the die, 
 the exposed pad comprises a plurality of openings through the exposed pad within a perimeter of the die, and 
 the die is exposed through the plurality of openings. 
   
     
     
         2 . The packaged semiconductor device of  claim 1 , wherein
 the die attach material comprises a solder die attach material.   
     
     
         3 . The packaged semiconductor device of  claim 1 , wherein
 the die attach material is patterned with a second plurality of openings that are aligned to the plurality of openings.   
     
     
         4 . The packaged semiconductor device of  claim 1 , wherein
 a solderable surface of the die is exposed through the plurality of openings.   
     
     
         5 . The packaged semiconductor device of  claim 1 , wherein
 the die comprises a plurality of recesses on the backside surface of the die, and   the plurality of recesses are aligned with the plurality of openings.   
     
     
         6 . The packaged semiconductor device of  claim 5 , wherein
 each of the plurality of recesses includes a solderable surface of the die, and   solderable surfaces of the plurality of recesses are exposed through the plurality of openings.   
     
     
         7 . The packaged semiconductor device of  claim 1 , further comprising:
 a plurality of solder structures joined to the die through the plurality of openings.   
     
     
         8 . The packaged semiconductor device of  claim 7 , wherein
 the plurality of solder structures are further joined to sides of the plurality of openings.   
     
     
         9 . The packaged semiconductor device of  claim 7 , wherein
 at least one of the plurality of solder structures is further joined to at least a portion of a second surface of the exposed pad, and   the second surface of the exposed pad is opposite the first surface of the exposed pad.   
     
     
         10 . The packaged semiconductor device of  claim 1 , wherein
 a second surface of the exposed pad is joined to a solderable surface of a package mounting structure, and   the second surface of the exposed pad is opposite the first surface of the exposed pad.   
     
     
         11 . The packaged semiconductor device of  claim 10 , further comprising:
 a solder layer joined to the second surface of the exposed pad, wherein
 the solder layer is further joined to the solderable surface of the package mounting structure. 
   
     
     
         12 . The packaged semiconductor device of  claim 10 , wherein
 the package mounting structure comprises one of a metal pin, a printed circuit board, a heat sink, an antenna, and a structure having a solderable surface.   
     
     
         13 . The packaged semiconductor device of  claim 1 , wherein
 the die comprises one of a semiconductor die, a gauge, a sensor device, and a sensor die.   
     
     
         14 . The packaged semiconductor device of  claim 5 , wherein
 at least one of the plurality of recesses is located adjacent to a heat-producing area of the die.   
     
     
         15 . The packaged semiconductor device of  claim 5 , wherein
 each of the plurality of recesses has an opening into the backside surface of the die, and   each opening has a cross-sectional area bounded by at least one of a polygonal shape, a curved shape, and an amorphous shape.   
     
     
         16 . A packaged semiconductor device for a die comprising:
 an exposed structure, wherein
 the die has an active surface and a backside surface opposite the active surface, 
 a first surface of the exposed structure is joined to die attach material, 
 the die attach material is further joined to the backside surface of the die, 
 the exposed structure comprises a plurality of openings through the exposed structure within a perimeter of the die, and 
 the die is exposed through the plurality of openings. 
   
     
     
         17 . The packaged semiconductor device of  claim 16 , wherein
 the exposed structure comprises one of a heat sink, an exposed pad of a lead frame, a metal pin, an antenna, and a structure having a solderable surface, and   the die attach material comprises thermal interface material.   
     
     
         18 . The packaged semiconductor device of  claim 17 , wherein
 the thermal interface material comprises a solder material, and   the thermal interface material is patterned with a second plurality of openings that are aligned to the plurality of openings.   
     
     
         19 . The packaged semiconductor device of  claim 16 , wherein
 the die comprises a plurality of recesses on the backside surface of the die, and   the plurality of recesses are aligned with the plurality of openings.   
     
     
         20 . The packaged semiconductor device of  claim 16 , wherein
 one or more solderable surfaces of the die are exposed through the plurality of openings, and   a plurality of solder structures are joined to the die through the plurality of openings.