Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure

Abstract

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

1 . An electrode structure comprising:
 a first polysilicon layer doped with resistance adjustment impurities;   a second polysilicon layer for adjusting grains, formed in the first polysilicon layer doped with the resistance adjustment impurities and additionally doped with grain adjustment impurities;   an ohmic metal layer formed on the first and second polysilicon layers;   a barrier metal layer formed on the ohmic metal layer; and   a metal layer formed on the barrier metal layer.   
     
     
         2 . The electrode structure of  claim 1 , wherein the second polysilicon layer is disposed between the first polysilicon layer and the ohmic metal layer. 
     
     
         3 . The electrode structure of  claim 2 , wherein the second polysilicon layer is uniformly formed on the first polysilicon layer. 
     
     
         4 . The electrode structure of  claim 1 , wherein the second polysilicon layer is formed in a specific level of the first polysilicon layer. 
     
     
         5 . The electrode structure of  claim 4 , wherein the second polysilicon layer is uniformly formed in the first polysilicon layer. 
     
     
         6 . The electrode structure of  claim 1 , wherein the second polysilicon layer is formed in the entire first polysilicon layer so that the second polysilicon layer and the first polysilicon are formed as a single polysilicon layer. 
     
     
         7 . The electrode structure of  claim 1 , wherein the grain adjustment impurities doped in the second polysilicon layer include one or more of carbon, nitrogen, and oxygen. 
     
     
         8 . The electrode structure of  claim 1 , wherein the ohmic metal layer is a metal silicide layer. 
     
     
         9 . The electrode structure of  claim 1 , wherein the grain adjustment impurities are a different type of impurity from the resistance adjustment impurities. 
     
     
         10 . The electrode structure of  claim 1 , wherein a grain size of grains in the second polysilicon layer is smaller than a grain size of grains in the first polysilicon layer. 
     
     
         11 . The electrode structure of  claim 1 , wherein, as a result of the grain adjustment impurities, an average grain size of grains in the second polysilicon layer is less than 50% of the average grain size of grains in the first polysilicon layer. 
     
     
         12 . The electrode structure of  claim 1 , wherein, as a result of the grain adjustment impurities, a thickness of the ohmic metal layer is reduced by at least 25% compared to if the grain adjustment impurities had not been included in the second polysilicon layer. 
     
     
         13 - 33 . (canceled) 
     
     
         34 . An electrode structure for a semiconductor device, the electrode structure comprising:
 a first polysilicon layer disposed on an insulating layer, the first polysilicon layer including resistance adjustment impurities;   a second polysilicon layer disposed on the first polysilicon layer, the second polysilicon layer including the resistance adjustment impurities and additional grain adjustment impurities, wherein the resistance adjustment impurities are a different type of impurity from the grain adjustment impurities, and wherein the second polysilicon layer has a higher grain concentration than the first polysilicon layer; and   one or more metal layers formed on the second polysilicon layer,   wherein the first polysilicon layer is disposed between the insulating layer and the second polysilicon layer, and   the second polysilicon layer is disposed between the first polysilicon layer and the one or more metal layers.   
     
     
         35 . The electrode structure of  claim 34 , wherein the one or more metal layers include:
 an ohmic metal layer formed on the second polysilicon layer;   a barrier metal layer formed on the ohmic metal layer, such that the ohmic metal layer is disposed between the second polysilicon layer and the barrier metal layer; and   a metal layer formed on the barrier metal layer, such that the barrier metal layer is disposed between the ohmic metal layer and the metal layer.   
     
     
         36 . The electrode structure of  claim 34 , wherein:
 the resistance adjustment impurities include one or more of carbon, nitrogen, and oxygen.   
     
     
         37 . The electrode structure of  claim 36 , wherein:
 the grain adjustment impurities include one or more of phosphorus, arsenic, or boron.   
     
     
         38 . The electrode structure of  claim 34 , wherein:
 the electrode structure is part of a first gate disposed on an N-doped region of the semiconductor device.   
     
     
         39 . The electrode structure of  claim 38 , further comprising:
 a second gate of the semiconductor device, the second gate including an additional electrode structure, the additional electrode structure including a respective first semiconductor layer, second semiconductor layer, and one or more metal layers corresponding to the respective layers of the electrode structure of the first gate,   wherein the second gate is disposed on a P-doped region of the semiconductor device, and   wherein the thicknesses of the layers of the electrode structure of the second gate are the same as respective thicknesses of the respective layers of the electrode structure of the first gate.   
     
     
         40 . An electrode structure for a semiconductor device, the electrode structure comprising:
 a first polysilicon layer disposed on an insulating layer, the first polysilicon layer including first impurities having a first impurity concentration;   a second polysilicon layer disposed on the first polysilicon layer, the second polysilicon layer including second impurities having a second impurity concentration higher than the first impurity concentration; and   one or more metal layers formed on the second polysilicon layer,   wherein the first polysilicon layer is disposed between the insulating layer and the second polysilicon layer, and   the second polysilicon layer is disposed between the first polysilicon layer and the one or more metal layers.   
     
     
         41 . The electrode structure of  claim 40 , wherein the first polysilicon layer is directly adjacent to the second polysilicon layer. 
     
     
         42 . The electrode structure of  claim 40 , further comprising:
 a third polysilicon layer disposed between the first polysilicon layer and the insulating layer and having the same impurity concentration as the second polysilicon layer.   
     
     
         43 . The electrode structure of  claim 40 , wherein:
 the second impurities include the first impurities and additional impurities.   
     
     
         44 . The electrode structure of  claim 43 , wherein:
 the first impurities include one or more of carbon, nitrogen, and oxygen; and   the additional impurities include one or more of phosphorus, arsenic, and boron.   
     
     
         45 . The electrode structure of  claim 40 , wherein:
 the second polysilicon layer has a lower grain size than the first polysilicon layer.   
     
     
         46 . The electrode structure of  claim 40 , wherein the one or more metal layers include:
 an ohmic metal layer formed on the second polysilicon layer;   a barrier metal layer formed on the ohmic metal layer, such that the ohmic metal layer is disposed between the second polysilicon layer and the barrier metal layer; and   a metal layer formed on the barrier metal layer, such that the barrier metal layer is disposed between the ohmic metal layer and the metal layer.