Low voltage difference operated eeprom and operating method thereof

Abstract

The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. In addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.

1 . A low voltage difference-operated electrically erasable programmable read only memory(EEPROM) comprising:
 a semiconductor substrate; and   at least one transistor structure formed in said semiconductor substrate and including a first dielectric layer formed on a surface of said semiconductor substrate, a first electric-conduction gate formed on said first dielectric layer, and at least two first ion-doped regions formed inside said semiconductor substrate and located at two sides of said first electric-conduction gate to function as a source and a drain,   wherein regions of said first ion-doped regions or a region of said semiconductor substrate, which is near an interface of said source and said first electric-conduction gate and an interface of said drain and said first electric-conduction gate, is further implanted with the same type of ions to increase ion concentration thereof and reduce voltage differences required for writing or erasing.   
     
     
         2 . The low voltage difference-operated EEPROM according to  claim 1  further comprising a capacitor structure formed in said semiconductor substrate and separated from said at least one transistor structure, wherein said capacitor structure includes a second ion-doped region formed inside said semiconductor substrate, a second dielectric layer formed on a surface of said second ion-doped region, and a second electric-conduction gate stacked on said second dielectric layer, and wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate. 
     
     
         3 . The low voltage difference-operated EEPROM according to  claim 1 , wherein said same type of ions are implanted into said semiconductor substrate or said first ion-doped regions to increase an ion concentration of said semiconductor substrate or said first ion-doped regions by 1-10 times. 
     
     
         4 . The low voltage difference-operated EEPROM according to  claim 2 , wherein said same type of ions are implanted into said semiconductor substrate or said first ion-doped regions to increase an ion concentration of said semiconductor substrate or said first ion-doped regions by 1-10 times. 
     
     
         5 . The low voltage difference-operated EEPROM according to  claim 1 , wherein while said transistor structure is an N-type transistor, said first ion-doped regions are N-type ion-doped regions, and said semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, and wherein while said transistor structure is a type transistor, said first ion-doped regions are P-type ion-doped regions, and said semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well. 
     
     
         6 . The low voltage difference-operated EEPROM according to  claim 2 , wherein while said transistor structure is an N-type transistor, said first ion-doped regions and said second ion-doped region are N-type ion-doped regions, and said semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, and wherein while said transistor structure is a P-type transistor, said first ion-doped regions and said second ion-doped region are P-type ion-doped regions, and said semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well. 
     
     
         7 . The low voltage difference-operated EEPROM according to  claim 1 , wherein spacers is formed between said first dielectric layer of said transistor structure or two side walls of said first electric-conduction gate. 
     
     
         8 . The low voltage difference-operated EEPROM according to  claim 7 , wherein before said spacers are formed, said first ion-doped regions, which are near said interface of said source and said first electric-conduction gate and said interface of said drain and said first electric-conduction gate, are further implanted with said same type of ions to increase an ion concentration of said first ion-doped regions. 
     
     
         9 . The low voltage difference-operated EEPROM according to  claim 1 , wherein said first electric-conduction gate includes a floating gate, a control dielectric layer and a control gate, which are bottom-up stacked over said first dielectric layer sequentially. 
     
     
         10 . The low voltage difference-operated EEPROM according to  claim 1 , wherein while said first ion-doped regions are further implanted with said same type of ions to increase an ion concentration of said first ion-doped regions, a voltage difference is applied to said transistor structure and said first electric-conduction gate for writing or erasing. 
     
     
         11 . The low voltage difference-operated EEPROM according to  claim 2 , wherein while said first ion-doped regions are further implanted with said same type of ions to increase an ion concentration of said first ion-doped regions, a voltage difference is applied to said transistor structure and said single floating gate for writing or erasing. 
     
     
         12 . The low voltage difference-operated EEPROM according to  claim 1 , wherein while said semiconductor substrate is further implanted with said same type of ions to increase an ion concentration of said semiconductor substrate, a voltage difference is applied to said semiconductor substrate and said first electric-conduction gate for writing or erasing. 
     
     
         13 . The low voltage difference-operated EEPROM according to  claim 2 , wherein while said semiconductor substrate is further implanted with said same type of ions to increase an ion concentration of said semiconductor substrate, a voltage difference is applied to said semiconductor substrate and said single floating gate for writing or erasing. 
     
     
         14 . The low voltage difference-operated EEPROM according to  claim 1 , wherein said transistor structure is a metal-oxide-semiconductor field-effect transistor (MOSFET). 
     
     
         15 . The low voltage difference-operated EEPROM according to  claim 1 , wherein a lightly-doped drain (LDD) is formed in said first ion-doped region. 
     
     
         16 . An operating method for a low voltage difference-operated electrically erasable programmable read only memory (EEPROM), wherein said low voltage difference-operated electrically erasable programmable read only memory comprises a semiconductor substrate and at least one N-type transistor structure formed in said semiconductor substrate, and wherein said N-type transistor structure includes a first electric-conduction gate and at least two first ion-doped regions formed inside said semiconductor substrate and located at two sides of said first electric-conduction gate to function as a source and a drain, and wherein regions of said first ion-doped regions, which are near an interface of said source and said first electric-conduction gate and an interface of said drain and said first electric-conduction gate, are further implanted with the same type of ions to increase an ion concentration of said regions of said first ion-doped regions, and wherein said method comprises a step:
 respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to said first electric-conduction gate, said source, said drain and said semiconductor substrate,   wherein in writing, Vsub=ground, Vs=Vd ≧0, and Vg=HV (High Voltage), or Vsub=ground, Vs=Vd=HV, and Vg>2V, and   wherein in erasing, Vsub=ground, Vs=Vd=HV, and Vg=0, a floating voltage, or <2V.   
     
     
         17 . The operating method for a low voltage difference-operated EEPROM according to  claim 16 , wherein said electrically erasable programmable read only memory further comprises a capacitor structure formed in said semiconductor substrate and separated from said at least one N-type transistor structure, and wherein said capacitor structure includes a second ion-doped region formed inside said semiconductor substrate and a second electric-conduction gate, and wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate, and wherein said gate voltage Vg is applied to said single floating gate. 
     
     
         18 . An operating method for a low voltage difference-operated electrically erasable programmable read only memory (EEPROM), wherein said low voltage difference-operated electrically erasable programmable read only memory comprises a semiconductor substrate and at least one P-type transistor structure formed in said semiconductor substrate, and wherein said P-type transistor structure includes a first electric-conduction gate and at least two first ion-doped regions formed inside said semiconductor substrate and located at two sides of said first electric-conduction gate to function as a source and a drain, and wherein regions of said first ion-doped regions, which are near an interface of said source and said first electric-conduction gate and an interface of said drain and said first electric-conduction gate, are further implanted with the same type of ions to increase an ion concentration of said regions of said first ion-doped regions, and wherein said method comprises a step:
 respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to said first electric-conduction gate, said source, said drain and said semiconductor substrate,   wherein in writing, Vsub=HV (High Voltage), Vs=Vd≦HV, and Vg=0, or Vsub=HV, Vs=Vd=0, and Vg is smaller than HV=2V, and   wherein in erasing, Vsub=HV, Vs=Vd=0, and Vg is a floating voltage or smaller than HV=2V.   
     
     
         19 . The operating method for a low voltage difference-operated EEPROM according to  claim 18 , wherein said electrically erasable programmable read only memory further comprises a capacitor structure formed in said semiconductor substrate and separated from said at least one P-type transistor structure, and wherein said capacitor structure includes a second ion-doped region fowled inside said semiconductor substrate and a second electric-conduction gate, and wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate, and wherein said gate voltage Vg is applied to said single floating gate. 
     
     
         20 - 23 . (canceled)