Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a package trace layout comprising a plurality of package traces;   an insulating layer having a first surface and a second surface opposite the first surface, wherein the plurality of package traces are embedded in the insulating layer between the first surface and the second surface, the package trace layout is entirely exposed on the first surface of the insulating layer;   wherein the package trace layout further comprises at least two different patterns of conductive dots on the first surface of the insulating layer that is used to connect to semiconductor chips of different sizes.   
     
     
         2 . The semiconductor package according to  claim 1 , wherein one or more package traces comprise at least two conductive dots and each conductive dot corresponds to a different pattern of conductive dots for connecting to semiconductor chips of different sizes. 
     
     
         3 . The semiconductor package according to  claim 1 , wherein the plurality of package traces is mutually isolated from one another.