Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a strain-relaxed buffer layer on the substrate;   a first well in the strain-relaxed buffer layer and located in a first region of the device;   a second well in the strain-relaxed buffer layer and located in a second region of the device;   a first channel layer on the first well; and   a second channel layer on the second well, and   wherein a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, and a lattice constant of material constituting the second channel layer is greater than said lattice constant of the material constituting the strain-relaxed buffer layer.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , further comprising a device isolation region comprising insulation material in the strain-relaxed buffer layer at a boundary between the first region and the second region, and
 wherein the bottom surface of the device isolation region is disposed above the upper surface of the substrate.   
     
     
         3 . The semiconductor device as claimed in  claim 2 , wherein the first well is a p-type well and the second well is an n-type well, and lowermost bounds of the wells are each disposed at a level below the level of the bottom surface of the device isolation region. 
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs). 
     
     
         6 . The semiconductor device as claimed in  claim 4 , wherein the first channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si). 
     
     
         7 . The semiconductor device as claimed in  claim 4 , wherein the second channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge). 
     
     
         8 . The semiconductor device as claimed in  claim 1 , wherein the first and second channel layers each have a thickness of 25 to 35 nm. 
     
     
         9 . The semiconductor device as claimed in  claim 1 , wherein the strain-relaxed buffer layer comprises Si (1-x) Ge x , the first channel layer comprises Si (1-y) Ge y , and the second channel layer comprises Si (1-z) Ge z ,
 wherein y and z are greater than or equal to 0 but less than or equal to 1, respectively, and   x is greater than y but less than z.   
     
     
         10 . The semiconductor device as claimed in  claim 9 , wherein x minus y is in a range of 0.2 to 0.4. 
     
     
         11 . The semiconductor device as claimed in  claim 9 , wherein z minus x is in a range of 0.2 to 0.4.