Stack type image sensor

Abstract

A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

What is claimed is: 
     
         1 . A stack type image sensor comprising:
 a first image sensor unit that comprises a via isolation trench penetrating from a first surface of a first substrate to a second surface of the first substrate opposite to the first surface, a via isolation layer including an insulation material formed in the via isolation trench, a first landing pad insulated by a first insulation layer formed on the second surface of the first substrate, and a first junction insulation layer disposed on the first landing pad and the first insulation layer;   a second image sensor unit that comprises a second landing pad, which is insulated by a second insulation layer formed on a second substrate, and a second junction insulation layer which is disposed on the second landing pad and the second insulation layer and contacts the first junction insulation layer; and   a through via that is insulated from one or more circuits of the first substrate by the via isolation layer and electrically connects the first landing pad to the second landing pad,   wherein each of the via isolation trench and the through via includes a first conductive layer.   
     
     
         2 . The stack type image sensor of  claim 1 , wherein the via isolation layer is formed to pass through from the first surface to the second surface of the first substrate. 
     
     
         3 . The stack type image sensor of  claim 1 , wherein:
 the first image sensor unit further comprises one or more transistors isolated from each other by a first device isolation layer disposed on the second surface of the first substrate,   the second image sensor unit further comprises one or more transistors isolated from each other by a second device isolation layer disposed on a first surface of the second substrate, and   the via isolation layer is formed to pass through from the first surface of the first substrate to the first device isolation layer.   
     
     
         4 . The stack type image sensor of  claim 1 , wherein the via isolation layer is formed on the first surface of the first substrate. 
     
     
         5 . The stack type image sensor of  claim 1 , wherein the via isolation layer is formed on an inner wall of the via isolation trench. 
     
     
         6 . The stack type image sensor of  claim 1 , wherein the first image sensor unit incudes a pixel circuit. 
     
     
         7 . The stack type image sensor of  claim 6 , wherein the second image sensor unit includes a logic circuit driving the pixel circuit. 
     
     
         8 . The stack type image sensor of  claim 1 , wherein the through via is buried in a via trench which passes through the first substrate, the first insulation layer, the first junction insulation layer, and the second junction insulation layer and exposes the first and second landing pads. 
     
     
         9 . The stack type image sensor of  claim 1 , wherein the through via is buried in a first via trench, which passes through the first substrate, the first insulation layer, the first junction insulation layer, and the second junction insulation layer and exposes the second landing pad, and a second via trench which passes through the first substrate and the first insulation layer and exposes the first landing pad. 
     
     
         10 . The stack type image sensor of  claim 1 , wherein the through via is buried in a via trench, which passes through the first substrate, the first insulation layer, the first landing pad, the first junction insulation layer, and the second junction insulation layer and exposes the first and second landing pads. 
     
     
         11 . The stack type image sensor of  claim 1 , wherein the through via is formed on an inner wall of a via trench, which passes through the first substrate, the first insulation layer, the first landing pad, the first junction insulation layer, and the second junction insulation layer and exposes the first and second landing pads. 
     
     
         12 . The stack type image sensor of  claim 1 , further comprising:
 a crack propagation stopper layer formed in the first substrate, the first insulation layer, the first junction insulation layer, the second junction insulation layer, the second insulation layer, and the second substrate to prevent crack propagation.   
     
     
         13 . A stack type image sensor comprising:
 a first image sensor unit that comprises a via isolation trench penetrating from a first surface of a first substrate to a second surface of the first substrate opposite to the first surface, a via isolation layer including an insulation material formed in the via isolation trench, a first insulation layer which is disposed on the first substrate and via isolation layer of the second surface of the first substrate, a first landing pad which is disposed in the first insulation layer, a first junction insulation layer which is disposed on the first landing pad and the first insulation layer, and a pixel circuit;   a second image sensor unit that comprises a second insulation layer which is disposed on a second substrate, a second landing pad which is disposed in the second insulation layer, a second junction insulation layer which is disposed on the second landing pad and the second insulation layer and contacts the first junction insulation layer, and a logic circuit;   a through via that is surrounded by the via isolation layer and electrically connects the first landing pad to the second landing pad; and   an external connection through via that is connected to the first landing pad or the second landing pad,   wherein each of the via isolation trench and the through via includes a first conductive layer.   
     
     
         14 . The stack type image sensor of  claim 13 , wherein the external connection through via is buried in an external connection via trench which passes through the first substrate, the first insulation layer, the first junction insulation layer, and the second junction insulation layer and exposes an external connection second landing pad having a same level as a level of the second landing pad. 
     
     
         15 . The stack type image sensor of  claim 13 , wherein the external connection through via is buried in an external connection via trench which passes through the first substrate and the first insulation layer and exposes an external connection first landing pad having a same level as a level of the first landing pad. 
     
     
         16 . A semiconductor device comprising:
 a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer;   a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer;   a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and   a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer,   wherein the third conductive layer is formed in the via isolation trench.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising:
 a second via trench penetrating the first substrate to expose the first conductive layer or the second conductive layer; and   a second through via formed in the second via trench, and including a fourth conductive layer insulated from the first substrate by the via isolation layer, the fourth conductive layer electrically connecting the first conductive layer or the second conductive layer.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the first through via further includes a fifth conductive layer on the third conductive layer. 
     
     
         19 . The semiconductor device of  claim 16 , further comprising:
 an anti-moisture-absorption layer included in the first through via.   
     
     
         20 . The semiconductor device of  claim 16 , wherein the first chip includes an array of pixels, the second chip includes a processing circuit for the first chip, and the first through via provides a signal transmission path between pixels of the first chip to processing circuitry of the second chip.