Semiconductor package structure

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

What is claimed is: 
     
         1 . A semiconductor package structure, comprising:
 a semiconductor chip;   a guard ring disposed on the semiconductor chip;   a gel layer disposed on the guard ring; and   a first lead frame electrically connected to the semiconductor chip, wherein the gel layer is located between the guard ring and the first lead frame.   
     
     
         2 . The semiconductor package structure according to  claim 1 , wherein the gel layer covers a side surface of the guard ring and a side surface of the semiconductor chip. 
     
     
         3 . The semiconductor package structure according to  claim 1 , wherein the gel layer fully covers the guard ring. 
     
     
         4 . The semiconductor package structure according to  claim 1 , wherein the gel layer comprises at least one of silicon gel and epoxy resin. 
     
     
         5 . The semiconductor package structure according to  claim 1 , wherein the semiconductor chip is a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), or a diode. 
     
     
         6 . The semiconductor package structure according to  claim 1 , further comprising:
 a solder disposed on the semiconductor chip, wherein the semiconductor chip is electrically connected to the first lead frame through the solder.   
     
     
         7 . The semiconductor package structure according to  claim 6 , wherein the solder comprises at least one of a lead-free solder, a dual-phase solid-liquid interdiffusion (SLID) bonding, a high-lead solder, and a nano-sized silver sintered material. 
     
     
         8 . The semiconductor package structure according to  claim 1 , wherein the first lead frame has a first width, a region of the semiconductor chip is exposed from the guard ring and has a second width along the direction of the first width, and the first width is about 40-100% of the second width. 
     
     
         9 . The semiconductor package structure according to  claim 1 , further comprising:
 a substrate; and   a second lead frame, wherein a gate contact of the semiconductor chip is electrically connected to the substrate through the second lead frame.   
     
     
         10 . The semiconductor package structure according to  claim 1 , further comprising:
 a substrate;   a housing for accommodating the substrate and the semiconductor chip;   an electrode layer disposed on the housing; and   a third lead frame, wherein the substrate is electrically connected to the electrode layer on the housing through the third lead frame.   
     
     
         11 . The semiconductor package structure according to  claim 1 , further comprising:
 a substrate; and   a third lead frame, wherein the substrate is electrically connected to an external power source through the third lead frame.   
     
     
         12 . A semiconductor package structure, comprising:
 a semiconductor chip;   a guard ring disposed on the semiconductor chip;   a solder disposed on the semiconductor chip;   a first lead frame electrically connected to the semiconductor chip through the solder; and   a gel layer disposed on the semiconductor chip and located between the semiconductor chip and the first lead frame, wherein a height of the gel layer is equal to or larger than a height of the solder.   
     
     
         13 . The semiconductor package structure according to  claim 12 , wherein the gel layer is located between the guard ring and the solder. 
     
     
         14 . The semiconductor package structure according to  claim 12 , wherein the gel layer comprises at least one of silicon gel and epoxy resin. 
     
     
         15 . The semiconductor package structure according to  claim 12 , wherein the semiconductor chip is a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), or a diode. 
     
     
         16 . The semiconductor package structure according to  claim 12 , wherein the solder comprises at least one of a lead-free solder, a dual-phase solid-liquid interdiffusion (SLID) bonding, a high-lead solder, and a nano-sized silver sintered material. 
     
     
         17 . The semiconductor package structure according to  claim 12 , wherein the first lead frame has a first width, a region of the semiconductor chip is exposed from the guard ring and has a second width along the direction of the first width, and the first width is about 40-100% of the second width. 
     
     
         18 . The semiconductor package structure according to  claim 12 , further comprising:
 a substrate; and   a second lead frame, wherein a gate contact of the semiconductor chip is electrically connected to the substrate through the second lead frame.   
     
     
         19 . The semiconductor package structure according to  claim 12 , further comprising:
 a substrate;   a housing for accommodating the substrate and the semiconductor chip;   an electrode layer disposed on the housing; and   a third lead frame, wherein the substrate is electrically connected to the electrode layer on the housing through the third lead frame.   
     
     
         20 . The semiconductor package structure according to  claim 12 , further comprising:
 a substrate; and   a third lead frame, wherein the substrate is electrically connected to an external power source through the third lead frame.