High power gallium nitride electronics using miscut substrates

Abstract

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

What is claimed is: 
     
         1 . A method of fabricating an electronic device, the method comprising:
 providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°;   growing a first III-V epitaxial layer coupled to the III-V substrate;   growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer;   forming a first contact in electrical contact with the III-V substrate; and   forming a second contact in electrical contact with the second III-V epitaxial layer.   
     
     
         2 . The method of  claim 1  wherein the normal to the growth surface is misoriented towards the negative <1 1 00> direction. 
     
     
         3 . The method of  claim 2  wherein the misorientation is between 0.4° and 0.5°. 
     
     
         4 . The method of  claim 1  wherein the normal to the growth surface is characterized by a misorientation towards the <11 2 0> direction of substantially zero degrees. 
     
     
         5 . The method of  claim 1  wherein the III-V substrate comprises an n-type GaN substrate. 
     
     
         6 . The method of  claim 1  wherein the first III-V epitaxial layer comprises an n-type GaN epitaxial layer having a thickness greater than 3 μm and the second III-V epitaxial layer comprises a p-type GaN epitaxial layer. 
     
     
         7 . The method of  claim 6  wherein the n-type GaN epitaxial layer has a thickness greater than 5 μm. 
     
     
         8 . The method of  claim 1  wherein the electronic device comprises a PN diode, the first contact comprises a cathode, and the second contact comprises an anode. 
     
     
         9 . The method of  claim 1  further comprising forming an isolation region disposed laterally to the second III-V epitaxial layer. 
     
     
         10 . The method of  claim 1  further comprising forming a third III-V epitaxial layer disposed between the second III-V epitaxial layer and the second contact, wherein a doping density of the third III-V epitaxial layer is higher than a doping density of the second III-V epitaxial layer.