Connection member, semiconductor device, and stacked structure

Abstract

A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

1 - 4 . (canceled) 
     
     
         5 . A semiconductor device comprising a connection member,
 the connection member including:   a dielectric material;   a penetrating via penetrating through the dielectric material;   a first metal plane provided in the dielectric material being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via; and   a second metal plane provided in or on the dielectric material, the second metal plane provided in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.   
     
     
         6 . The semiconductor device according to  claim 5  further comprising:
 a plurality of semiconductor chips including a high frequency chip; 
 a resin layer adhering the plurality of semiconductor chips and the connection member with each other; and 
 a wiring layer formed on the plurality of semiconductor chips and the connection member, the wiring layer electrically connect the plurality of semiconductor chips and the connection member. 
 
     
     
         7 . The semiconductor device according to  claim 6  further comprising an antenna provided on the wiring layer. 
     
     
         8 . A stacked structure comprising:
 a connection member including
 a dielectric material, 
 a penetrating via penetrating through the dielectric material, 
 a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and 
 a second metal plane provided in or on the dielectric material, the a second metal plane provided in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane; and 
   a first circuit board electrically connected to the connection member.   
     
     
         9 . The stacked structure according to  claim 8  further comprising a second circuit board under the first circuit board,
 wherein the connection member is provided between the first circuit board and the second circuit board, and 
 the first circuit board and the second circuit board are electrically connected by the connection member. 
 
     
     
         10 . The stacked structure according to  claim 8  further comprising an EBG structure body above the first circuit board,
 wherein the connection member is provided between the first circuit board and the EBG structure body, and 
 the first circuit board and the EBG structure body are electrically connected by the connection member. 
 
     
     
         11 . A connection member comprising:
 a metal plane;   a first dielectric material covering the metal plane;   a metal patch provided with the first dielectric material interposed between the metal patch and the metal plane;   a connection via provided in the first dielectric material, the connection via connecting the metal plane and the metal patch; and   a first signal line extending in a direction perpendicular to an extension direction of the connection via.   
     
     
         12 . The connection member according to  claim 11  further comprising a second dielectric material covering the metal patch,
 wherein the first signal line is in contact with the first dielectric material or the second dielectric material. 
 
     
     
         13 . The connection member according to  claim 12  further comprising a second signal line and a third signal line extending in a direction perpendicular to the connection via,
 wherein the first signal line is provided with the first dielectric material interposed between the first signal line and the connection via, 
 the second signal line is provided with the second dielectric material interposed between the second signal line and the metal patch, and 
 the third signal line is provided with the connection via and the first dielectric material interposed between the third signal line and the first signal line. 
 
     
     
         14 . A semiconductor device comprising a connection member,
 the connection member including:   a metal plane;   a first dielectric material covering the metal plane;   a metal patch provided with the first dielectric material interposed between the metal patch and the metal plane;   a connection via provided in the first dielectric material, the connection via connecting the metal plane and the metal patch; and   a first signal line extending in a direction perpendicular to an extension direction of the connection via.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the connection member further includes a second dielectric material covering the metal patch, and
 the first signal line is in contact with the first dielectric material or the second dielectric material.   
     
     
         16 . The semiconductor device according to  claim 15 , wherein the connection member further includes a second signal line and a third signal line extending in a direction perpendicular to the connection via,
 the first signal line is provided with the first dielectric material interposed between the first signal line and the connection via,   the second signal line is provided with the second dielectric material interposed between the second signal line and the metal patch, and   the third signal line is provided with the connection via and the first dielectric material interposed between the third signal line and the first signal line.   
     
     
         17 . A stacked structure comprising:
 a connection member including
 a metal plane, 
 a first dielectric material covering the metal plane, 
 a metal patch provided with the first dielectric material interposed between the metal patch and the metal plane, 
 a connection via provided in the first dielectric material, the connection via connecting the metal plane and the metal patch, and 
 a first signal line extending in a direction perpendicular to an extension direction of the connection via; and 
   a first circuit board electrically connected to the connection member.   
     
     
         18 . The stacked structure according to  claim 17 , wherein the connection member further includes a second dielectric material covering the metal patch,
 wherein the first signal line is provided in contact with the first dielectric material or the second dielectric material.   
     
     
         19 . The stacked structure according to  claim 17  further comprising a second circuit board under the first circuit board,
 wherein the connection member is provided between the first circuit board and the second circuit board, and 
 the first circuit board and the second circuit board are electrically connected by the connection member. 
 
     
     
         20 . The stacked structure according to  claim 17  further comprising a shielding wall provided on an external periphery of the first circuit board,
 wherein the shielding wall has a structure in which the connection member and an EBG member are arranged alternately, 
 wherein the EBG member includes: 
 a second metal plane; 
 a third dielectric material covering the second metal plane; 
 a second metal patch provided with the third dielectric material interposed between the second metal patch and the second metal plane; and 
 a second connection via provided in the third dielectric material, the second connection via connecting the second metal plane and the second metal patch, and 
 wherein the connection member is arranged in such orientation that the first metal patch faces an outside of the first circuit board with respect to the first metal plane, and 
 the EBG member is arranged in such orientation that the second metal patch faces an inner side of the first circuit board with respect to the second metal plane. 
 
     
     
         21 . The stacked structure according to  claim 19  further comprising a shielding wall provided on an external periphery of the second circuit board,
 wherein the shielding wall has a structure in which the connection member and an EBG member are arranged alternately, 
 wherein the EBG member includes: 
 a second metal plane; 
 a third dielectric material covering the second metal plane; 
 a second metal patch provided with the third dielectric material interposed between the second metal patch and the second metal plane; and 
 a second connection via provided in the third dielectric material, the second connection via connecting the second metal plane and the second metal patch, and 
 wherein the connection member is arranged in such orientation that the first metal patch faces an outside of the first circuit board with respect to the first metal plane, and 
 the EBG member is arranged in such orientation that the second metal patch faces an inner side of the first circuit board with respect to the second metal plane. 
 
     
     
         22 . A semiconductor device comprising:
 a semiconductor chip;   an insulation layer provided on a peripheral portion of the semiconductor chip, the insulation layer having a dielectric constant less than that of the semiconductor chip, the insulation layer including an inclined surface extending from the peripheral portion of the semiconductor chip to an inner side;   a plurality of wiring layers formed on the inclined surface; and   a cap portion provided on the insulation layer, a hollow portion being formed between the cap portion and the semiconductor chip, wherein the cap portion has a penetrating via connected to the wiring layer, and a dielectric constant of the cap portion is higher than that of the insulation layer.   
     
     
         23 . The semiconductor device according to  claim 22 , wherein an inclination angle of the inclined surface with respect to a surface of the semiconductor chip is preferably equal to or less than 45 degrees. 
     
     
         24 . The semiconductor device according to  claim 22 , wherein the semiconductor chip includes a plurality of electrode pads, and
 the wiring layer is connected to the electrode pads.   
     
     
         25 . The semiconductor device according to  claim 22 , wherein the semiconductor chip is a high frequency chip.