Vertical transistor and the fabrication method

Abstract

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

What is claimed is: 
     
         1 . A vertical transistor comprising:
 a first surface and a second surface positioned opposite to the first surface;   a drift region with a first doping type, the drift region being located between the first surface and the second surface;   at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions;   at least one drain region with the first doping type and the drain region being located between said drift region and said second surface;   and a gate being provided between adjacent drain regions; the gate including a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface.   
     
     
         2 . The vertical transistor of  claim 1  further comprising a source electrode located on said first surface and the drain electrode on the second surface. 
     
     
         3 . The vertical transistor of  claim 1 , wherein the the first doping type is N-type. 
     
     
         4 . The vertical transistor of  claim 3 , wherein the drift region is N-type doped GaN, with a thickness of 2-50 μm. 
     
     
         5 . The vertical transistor of  claim 3 , wherein the source region is heavily doped N-type GaN and the drain region is with heavily doped N-type GaN. 
     
     
         6 . The vertical transistor of  claim 1 , wherein the gate electrode is selected from one of Ti, TiN, Ta, TaN, W, Al, Cu, Ag, Ni, Au, Cr, and polycrystalline silicon. 
     
     
         7 . The vertical transistor of  claim 1 , wherein the gate dielectric layer comprises silicon oxide and the thickness of the gate dielectric layer is about 2-50 nm. 
     
     
         8 . The vertical transistor of  claim 1 , wherein the dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm. 
     
     
         9 . The vertical transistor of  claim 1 , wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about  20 - 100 nm. 
     
     
         10 . A system comprising:
 an integrated circuit having:   a vertical transistor comprising:
 a first surface and a second surface positioned opposite to the first surface, 
 a drift region with a first doping type, the drift region being located between the first surface and the second surface, 
 at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions, 
 at least one drain region with the first doping type and the drain region being located between said drift region and said second surface, and 
 a gate being provided between adjacent drain regions; the gate including a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface. 
   
     
     
         12 . The system of  claim 10 , further comprising a source electrode located on said first surface and the drain electrode on the second surface. 
     
     
         13 . The system of  claim 10 , wherein the first doping type is N-type. 
     
     
         14 . The system of  claim 13 , wherein the drift region is N-type doped GaN, with a thickness of 2-50 μm. 
     
     
         15 . The system of  claim 13 , wherein the source region is heavily doped N-type GaN and the drain region is with heavily doped N-type GaN. 
     
     
         16 . The system of  claim 10 , wherein the gate electrode is selected from one of Ti, TiN, Ta, TaN, W, Al, Cu, Ag, Ni, Au, Cr, and polycrystalline silicon. 
     
     
         17 . The system of  claim 10 , wherein the gate dielectric layer comprises silicon oxide and the thickness of the gate dielectric layer is about 2-50 nm. 
     
     
         18 . The system of  claim 10 , wherein the dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm. 
     
     
         19 . The vertical transistor of  claim 1  wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm. 
     
     
         19 . The system of  claim 10 , wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm. 
     
     
         20 . A method for implementing a vertical transistor, the method comprising:
 providing a first surface and a second surface;   positioning the second surface opposite to the first surface;   providing a drift region with a first doping type;   positioning the drift region between the first surface and the second surface,
 wherein at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions, and 
 at least one drain region with the first doping type and the drain region being located between said drift region and said second surface; and 
   positioning a gate being between adjacent drain regions, wherein the gate includes a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface.