MOSFET Having Source Region Formed in a Double Wells Region

Abstract

A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region;   a first source region and the drain region on opposite sides of the first gate electrode;   a second source region and the drain region on opposite sides of the second gate electrode;   a first body contact region adjacent to the first source region;   a plurality of source regions and a plurality of body contact regions adjacent to the first body contact region, wherein the first source region, the first body contact region, the plurality of body contact regions and the plurality of source regions are formed in an alternating manner from a top view; and   a pickup ring surrounding the first source region, the second source region, the first gate electrode, the second gate electrode and the drain region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first source region formed in a first stacked well region, wherein the first stacked well region comprises:
 a first region over the substrate; and   a second region embedded in the first region, and wherein a doping density of the second region is greater than a doping density of the first region.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the second source region formed in a second stacked well region, wherein the second stacked well region comprises:
 a third region over the substrate; and   a fourth region embedded in the third region, and wherein a doping density of the fourth region is greater than a doping density of the third region.   
     
     
         4 . The semiconductor device of  claim 1 , wherein:
 the first source region, the first body contact region, the plurality of body contact regions and the plurality of source regions form a region rectangular in shape from the top view.   
     
     
         5 . The semiconductor device of  claim 4 , wherein:
 the region and the first gate electrode are parallel from the top view.   
     
     
         6 . The semiconductor device of  claim 1 , wherein:
 the first source region is an n-type region; and   the first body contact region is a p-type region.   
     
     
         7 . The semiconductor device of  claim 1 , wherein:
 each body contact region is in direct contact with two source regions.   
     
     
         8 . The semiconductor device of  claim 1 , wherein:
 the first source region and the pickup ring are separated by an isolation region; and   the first body contact region and the pickup ring are separated by the isolation region.   
     
     
         9 . The semiconductor device of  claim 1 , wherein:
 the pickup ring has a first sidewall in direct contact with a first isolation region and a second sidewall in direct contact with a second isolation region.   
     
     
         10 . The semiconductor device of  claim 9 , wherein:
 a bottom of the first isolation region is in direct contact with a first well; and   a bottom of the second isolation region is in direct contact with a second well, and wherein:
 the second well is embedded in the first well; and 
 a doping density of the second well is greater than a doping density of the first well. 
   
     
     
         11 . A device comprising:
 a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region;   a first source region and the drain region on opposite sides of the first gate electrode;   a second source region and the drain region on opposite sides of the second gate electrode;   a first doped well formed under the first source region;   a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well; and   a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.   
     
     
         12 . The device of  claim 11 , further comprising:
 a third doped well formed under the second source region; and   a fourth doped well formed under the second source region, wherein the third doped well is embedded in the fourth doped well, and wherein a doping density of the third doped well is greater than a doping density of the fourth doped well.   
     
     
         13 . The device of  claim 12 , wherein:
 a bottom of the third doped well is substantially level with a bottom of the first doped well; and   a bottom of the fourth doped well is substantially level with a bottom of the second doped well.   
     
     
         14 . The device of  claim 11 , further comprising:
 a pickup ring surrounding a first transistor formed by the first source region, the first gate electrode and the drain region, and a second transistor formed by the second source region, the second gate electrode and the drain region.   
     
     
         15 . The device of  claim 14 , wherein:
 the first source region, the second source region and the drain region are n-type regions; and   the body contact region and the pickup ring are p-type regions.   
     
     
         16 . An apparatus comprising:
 a first transistor comprising a first gate, a first source, a drain and a first body contact, wherein:
 the first body contact and the first source form a first column from a top view; and 
 the first source formed in a first stacked well region, wherein the first stacked well region comprises:
 a first region formed over a substrate; and 
 a second region embedded in the first region; 
 
   a second transistor comprising a second gate, a second source, the drain and a second body contact, and wherein:
 the second body contact and the second source form a second column from the top view; and 
 the second source formed in a second stacked well region, wherein the second stacked well region comprises:
 a third region over the substrate; and 
 a fourth region embedded in the third region; and 
 
   a pickup ring surrounding the first transistor and the second transistor.   
     
     
         17 . The apparatus of  claim 16 , wherein:
 a doping density of the second region is greater than a doping density of the first region; and   a doping density of the fourth region is greater than a doping density of the third region.   
     
     
         18 . The apparatus of  claim 16 , further comprising:
 a first lightly doped source/drain region adjacent to the first source in the second region.   
     
     
         19 . The apparatus of  claim 16 , further comprising:
 a second lightly doped drain/source region adjacent to the drain and formed in the substrate.   
     
     
         20 . The apparatus of  claim 16 , wherein:
 the first source, the second source and the drain are n-type regions; and   the first body contact, the second body contact and the pickup ring are p-type regions.