Isolated iii-n semiconductor devices

Abstract

A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

1 . A semiconductor device, comprising:
 a substrate of a first conductivity type;   a gallium-nitride layer formed over the substrate;   a barrier layer comprising III-N semiconductor material formed on the gallium-nitride layer;   a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate;   a source contact;   a drain contact;   a gate contact between the source contact and the drain contact;   a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and   a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a conductive via between the source contact and the doped layer. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a conductive via between the drain contact and the doped layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 
     
     
         5 . The semiconductor device of  claim 4 , further comprising a second transistor formed adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 
     
     
         6 . The semiconductor device of  claim 5 , further comprising a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the second transistor further comprises:
 a second source contact; and   a conductive member between the second source contact and the portion of doped layer.   
     
     
         8 . The semiconductor device of  claim 1 , further comprising an aluminum-nitride layer adjacent the doped layer. 
     
     
         9 . The semiconductor device of  claim 8 , further comprising a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 
     
     
         10 . The semiconductor device of  claim 9 , further comprising a gallium-nitride layer adjacent the buffer layer. 
     
     
         11 . A method of forming a semiconductor device, comprising:
 forming a gallium-nitride layer over a substrate, the substrate having a first conductivity type;   forming a barrier layer comprising III-N semiconductor material on the gallium nitride layer;   forming a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate;   forming a source contact;   forming a drain contact;   forming a gate contact between the source contact and the drain contact; and   forming a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and   forming a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer.   
     
     
         12 . The method of  claim 11 , further comprising forming a conductive via between the source contact and the doped layer. 
     
     
         13 . The method of  claim 11 , further comprising forming a conductive via between the drain contact and the doped layer. 
     
     
         14 . The method of  claim 11 , wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 
     
     
         15 . The method of  claim 14 , further comprising forming a second transistor adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 
     
     
         16 . The method of  claim 15 , further comprising forming a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 
     
     
         17 . The method of  claim 16 , wherein forming the second transistor further comprises:
 forming a second source contact; and   forming a conductive member between the second source contact and the portion of doped layer.   
     
     
         18 . The method of  claim 11 , further comprising forming an aluminum-nitride layer adjacent the doped layer. 
     
     
         19 . The method of  claim 18 , further comprising forming a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 
     
     
         20 . The method of  claim 19 , further comprising forming a gallium-nitride layer adjacent the buffer layer.