Soi substrate and manufacturing method thereof

Abstract

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

What is claimed is: 
     
         1 . A manufacturing method of a silicon on insulator substrate, comprising the steps of:
 providing a first semiconductor substrate;   growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer;   irradiating the first semiconductor substrate via a ion beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer;   providing a second substrate;   growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;   bonding the first wafer with second wafer through a hydrophilic bonding process, wherein the first wafer is bonded with second wafer at a temperature between 200 degrees centigrade and degrees centigrade, the detail steps of hydrophilic bonding process further comprises the steps of:   wetting the first insulating layer and the second insulating layer;   contacting the wetted first insulating layer with the wetted second insulating layer; and   pressing the first insulating layer and the second insulating layer for closely bonding the first insulating layer with the second insulating layer;   annealing the first wafer and second wafer;   separating a part of the first wafer from the second wafer; and   forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.   
     
     
         2 . The method according to  claim 1 , wherein a material of the first semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound. 
     
     
         3 . The method according to  claim 1 , wherein the pre-determined depth is between 0.1 μm and 5 μm. 
     
     
         4 . The method according to  claim 1 , wherein the deuterium and hydrogen co-doping layer is implanted at the first semiconductor substrate through a hydrogen and deuterium ions co-beam, and an accelerated voltage of the hydrogen and deuterium ions co-beam is between 1 keV and 200 keV and a doping dosage of the hydrogen and deuterium ions co-beam is between 10 16  ions/cm 2  and 2×10 17  ions/cm 2 . 
     
     
         5 . The method according to  claim 1 , wherein a material of the second semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound. 
     
     
         6 . The method according to  claim 1 , wherein the first wafer is boned with the second wafer face to face at a temperature between 200 degrees centigrade and 400 degrees centigrade. 
     
     
         7 . (canceled) 
     
     
         8 . The method according to  claim 1 , wherein the step of annealing the first wafer and second wafer further includes: heating the first wafer and the second wafer to a temperature between 600 degrees centigrade and 900 degrees centigrade; and cooling the first wafer and the second wafer to a temperature between 400 degrees centigrade and 600 degrees centigrade 
     
     
         9 . The method according to  claim 8 , wherein time for cooling the first wafer and the second wafer is between 30 minutes and 120 minutes. 
     
     
         10 . The method according to  claim 1 , wherein a thickness of the deuterium and hydrogen co-doping semiconductor layer is between 50 Å and 50000 Å. 
     
     
         11 . The method according to  claim 1 , further comprising a step of heating the second wafer to 10000 degrees centigrade once again after separating a part of the first wafer from the second wafer . 
     
     
         12 . The method according to  claim 11 , wherein time for heating the first wafer and the second wafer once again is between 30 minutes and 8 hours. 
     
     
         13 . A silicon on insulator substrate, comprising:
 a semiconductor substrate;   an insulating layer grown on a top surface of the semiconductor substrate; and   a deuterium and hydrogen co-doping semiconductor layer grown on a top surface of the insulating layer.   
     
     
         14 . The silicon on insulator substrate according to  claim 13 , wherein a material of the semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound. 
     
     
         15 . The silicon on insulator substrate according to  claim 13 , wherein a thickness of the deuterium and hydrogen co-doping semiconductor layer is between 50 Å and 50000 Å.