US2017263721A1PendingUtilityA1

Copper-filled trench contact for transistor performance improvement

Assignee: INTEL CORPPriority: Mar 30, 2006Filed: May 30, 2017Published: Sep 14, 2017
Est. expiryMar 30, 2026(expired)· nominal 20-yr term from priority
H10W 20/42H10W 20/051H10W 20/048H10W 20/044H10W 20/40H10W 20/033H01L 21/76843H01L 29/41725H01L 29/78H01L 29/456H01L 29/66477H10D 64/62H10D 62/83H10D 30/60H10D 30/021H10D 64/251
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Claims

Abstract

Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a gate electrode above a portion of a semiconductor substrate;   a source region in the semiconductor substrate, on a first side of the gate electrode;   a drain region in the semiconductor substrate, on a second side of the gate electrode, wherein the gate electrode has a gate length along a first direction taken from the source region to the drain region;   a trench contact connected to one of the source region or the drain region, the trench contact in a dielectric layer and laterally adjacent the gate electrode, wherein the dielectric layer is over the gate electrode, wherein the trench contact has a trench contact length greater than a trench contact width and has an uppermost surface substantially coplanar with an uppermost surface of the dielectric layer, and wherein the trench contact width is parallel with the first direction and the trench contact length is orthogonal to the first direction; and   a conductor structure on a portion of but not all of the trench contact and on a portion of the uppermost surface of the dielectric layer.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a metallization layer connected to the conductor structure, the metallization layer including dielectric material and one or more conductive lines within that dielectric material. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the metallization layer is over the entire conductor structure. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the trench contact length extends an entire length of at least one of the source region and the drain region. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the conductor structure extends from the trench contact onto an adjacent field of the semiconductor substrate. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein at least one of the source region and the drain region includes a conductive surface on the semiconductor substrate. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein the conductive surface comprises a silicide material. 
     
     
         8 . The semiconductor structure of  claim 6 , wherein the conductive surface comprises a doped region of the semiconductor substrate. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the trench contact comprises copper. 
     
     
         10 . The semiconductor structure of  claim 1 , further comprising a layer lining surfaces of the trench contact, the layer comprising copper and silicon. 
     
     
         11 . A method of forming a semiconductor structure, comprising:
 forming a gate electrode above a portion of a semiconductor substrate;   forming a source region in the semiconductor substrate, on a first side of the gate electrode;   forming a drain region in the semiconductor substrate, on a second side of the gate electrode, wherein the gate electrode has a gate length along a first direction taken from the source region to the drain region;   forming a trench contact connected to one of the source region or the drain region, the trench contact in a dielectric layer and laterally adjacent the gate electrode, wherein the dielectric layer is over the gate electrode, wherein the trench contact has a trench contact length greater than a trench contact width and has an uppermost surface substantially coplanar with an uppermost surface of the dielectric layer, and wherein the trench contact width is parallel with the first direction and the trench contact length is orthogonal to the first direction; and   forming a conductor structure on a portion of but not all of the trench contact and on a portion of the uppermost surface of the dielectric layer.   
     
     
         12 . The method of  claim 11 , wherein forming the conductor structure and the trench contact comprises a dual damascene process. 
     
     
         13 . The method of  claim 11 , wherein forming the trench contact and the conductor structure includes simultaneously filling the trench contact and the conductor structure with a conductive material. 
     
     
         14 . The method of  claim 13 , wherein the conductive material is copper. 
     
     
         15 . The method of  claim 11 , further comprising forming a metallization layer on a top surface of the conductor structure, the metallization layer including dielectric material and one or more conductive lines within that dielectric material. 
     
     
         16 . The method of  claim 15 , wherein forming the metallization layer and the conductor structure comprises a dual damascene process. 
     
     
         17 . The method of  claim 11 , further comprising forming a layer within trench sidewalls of the trench contact, wherein the layer comprises a silicide, and provides one or more of a diffusion barrier for copper and a nucleation layer for copper. 
     
     
         18 . The method of  claim 17 , wherein forming the trench contact includes forming a copper containing material on the layer within the trench sidewalls of the trench contact. 
     
     
         19 . The method of  claim 11 , wherein forming the trench contact comprises an electroless deposition process. 
     
     
         20 . The method of  claim 19 , further comprising performing a surface treatment to produce an activated surface of the trench contact.

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