Hybrid integration fabrication of nanowire gate-all-around ge pfet and polygonal iii-v pfet cmos device

Abstract

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

What is claimed is: 
     
         1 . A nanowire semiconductor device characterized in comprising:
 a substrate, said substrate including an active region of PMOS and an active region of NMOS;   forming a first nanowire in the active region of PMOS;   forming a second nanowire on the active region of NMOS; and   completely surrounding the first nanowire and partially surrounding the second nanowire with gate dielectric layer and the gate electrode layer.   
     
     
         2 . The nanowire semiconductor device according to  claim 1 , characterized in that the length of the first nanowire is in the range of between 2 nm to 50 nm, the diameter of said first nanowire is in the range of between 2 nm to 5 nanometers. 
     
     
         3 . The nanowire semiconductor device according to  claim 1 , wherein the first nanowire is germanium nanowire, the shape of the section of said germanium nanowire is circular, oval or prism;
 said second nanowire is InGaAs nanowire, the cross-sectional shape of said second nanowire is polygon.   
     
     
         4 . The nanowire semiconductor device according to  claim 3 , characterized in that the germanium content of the first nanowire is in the range of between 65% to 100%. 
     
     
         5 . The nanowire semiconductor device according to  claim 1 , wherein said gate dielectric layer is a high-k gate dielectric layer, the material of said gate dielectric layer material is Al 2 O 3  or TiSiO x . The gate electrode layer is a metal electrode layer, the material of said gate electrode layer is TiN, NiAu or one of CrAu. 
     
     
         6 . A method for implementing a nanowire semiconductor device, the method comprising:
 providing a substrate, said substrate including an active region of PMOS and an active region of NMOS;   forming a first nanowire in the active region of PMOS;   forming a second nanowire on the active region of NMOS; and   completely surrounding the first nanowire and partially surrounding the second nanowire with gate dielectric layer and the gate electrode layer.   
     
     
         7 . The method for implementing nanowire semiconductor device according to  claim 6 , characterized in that the length of the first nanowire is in the range of between 2 nm to 50 nm, the diameter of said first nanowire is in the range of between 2 nm to 5 nanometers. 
     
     
         8 . The method for implementing nanowire semiconductor device according to  claim 6 , wherein the first nanowire is germanium nanowire, the shape of the section of said germanium nanowire is circular, oval or prism;
 said second nanowire is InGaAs nanowire, the cross-sectional shape of said second nanowire is polygon.   
     
     
         9 . The method for implementing nanowire semiconductor device according to  claim 8 , characterized in that the germanium content of the first nanowire is in the range of between 65% to 100%. 
     
     
         10 . The method for implementing nanowire semiconductor device according to  claim 6 , wherein said gate dielectric layer is a high-k gate dielectric layer, the material of said gate dielectric layer material is Al 2 O 3  or TiSiO x . The gate electrode layer is a metal electrode layer, the material of said gate electrode layer is TiN, NiAu or one of CrAu.