Semiconductor device and method of fabricating the same

Abstract

Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, comprising:
 forming a sacrificial gate pattern on a substrate;   forming spacers on both sidewalls of the sacrificial gate pattern;   forming a first interlayered insulating layer to cover sidewalls of the spacers and expose top surfaces of the spacers;   replacing the sacrificial gate pattern with a preliminary gate electrode;   recessing the preliminary gate electrode and the spacers to form a gate electrode and define a recessed region on the gate electrode; and   forming a gate capping pattern to fill the recessed region and cover top and both side surfaces of the gate electrode.   
     
     
         2 . The method of  claim 1 , wherein the top surface of the gate electrode is higher than a lowermost bottom surface of the recessed region. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming epitaxial patterns on the substrate at both sides of the sacrificial gate pattern.   
     
     
         4 . The method of  claim 3 , further comprising:
 forming a second interlayered insulating layer on the first interlayered insulating layer to cover the gate capping pattern; and   forming contact plugs to penetrate the second and first interlayered insulating layers and be connected to the epitaxial patterns, respectively,   wherein each of the contact plugs is formed to be in contact with at least a portion of the gate capping pattern.   
     
     
         5 . The method of  claim 1 , wherein the forming of the gate capping pattern comprises:
 forming a gate capping insulating layer to conformally cover top and both side surfaces of the gate electrode and inner sidewalls of the recessed region; and   performing a planarization process on the gate capping insulating layer to form the gate capping pattern, a top surface of the gate capping pattern being coplanar with a top surface of the first interlayered insulating layer.   
     
     
         6 . The method of  claim 5 , wherein the gate capping insulating layer is formed using an atomic layer deposition process. 
     
     
         7 . The method of  claim 1 , wherein the recessing comprises:
 recessing a top portion of the preliminary gate electrode to form the gate electrode; and   recessing the spacers to form spacer structures,   wherein the recessed region is formed to expose both sidewalls of the gate electrode.   
     
     
         8 . The method of  claim 1 , wherein the recessing is performed to expose a portion of a top surface of the substrate. 
     
     
         9 . The method of  claim 1 , wherein the recessing comprises partially etching the first interlayered insulating layer in contact with the spacers, and
 the recessed region is formed to have an inclined inner sidewall.   
     
     
         10 . The method of  claim 9 , wherein the recessed region is formed to have a width increasing in a direction away from the substrate. 
     
     
         11 . The method of  claim 1 , wherein the spacers and the gate capping pattern are formed of different materials from each other. 
     
     
         12 . A method of fabricating a semiconductor device, comprising:
 forming a gate electrode on a substrate;   forming gate spacers on both sidewalls of the gate electrode;   forming a interlayered insulating layer on the substrate to cover the gate spacers;   recessing the gate electrode and the gate spacers to form a recess surrounded by the interlayered insulating layer; and   forming a gate capping layer filling the recess,   wherein the recess exposes a top surface and both upper side surfaces of the gate electrode.   
     
     
         13 . The method of  claim 12 , wherein the top surface of the gate electrode is higher than top surfaces of the gate spacers after the recessing. 
     
     
         14 . The method of  claim 12 , wherein the gate capping layer is conformally formed in the recess such that a seam is formed in an upper portion of the gate capping layer. 
     
     
         15 . The method of  claim 12 , further comprising:
 forming an active pattern vertically protruding from the substrate;   forming epitaxial patterns in upper portions of the active pattern,   wherein the gate electrode is formed to cross the active pattern.   
     
     
         16 . The method of  claim 12 , wherein the recessing of the gate spacers is performed until a portion of a top surface of the substrate is exposed. 
     
     
         17 . The method of  claim 12 , wherein the recessing comprises partially etching the interlayered insulating layer adjacent to the gate spacers, and
 the recess is formed to have an inclined inner sidewall.