High Performance, High Capacity Memory Systems and Modules

Abstract

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

What is claimed is: 
     
         1 . A motherboard comprising:
 a memory-controller component;   a first memory-module socket adjacent the memory-controller component;   a second memory-module socket adjacent the first memory-module socket on a side of the first memory-module socket opposite the memory-controller component;   a third memory-module socket adjacent the second memory-module socket on a side of the second memory-module socket opposite the first memory-module socket;   a fourth memory-module socket adjacent the third memory-module socket on a side of the third memory-module socket opposite the second memory-module socket;   a first data-link group coupling the memory-controller component to the first memory module socket and the third memory-module socket, the first data-link group extending past the second memory-module socket; and   a second data-link group extending past the first memory-module socket and the third memory-module socket, the second data-link group coupling the memory-controller component to the second memory module socket and the fourth memory-module socket.   
     
     
         2 . The motherboard of  claim 1 , further comprising a first memory module in the first memory-module socket and a second memory module in the second memory-module socket, the memory controller to direct a memory transaction to the first memory module and the second memory module via the respective first data-link group and the second data-link group. 
     
     
         3 . The motherboard of  claim 2 , further comprising a third memory module in the third memory-module socket and a fourth memory module in the fourth memory-module socket, the memory controller to direct the memory transaction to the third memory module and the fourth memory module via the respective second data-link group and the first data-link group. 
     
     
         4 . The motherboard of  claim 2 , each of the sockets including a similar arrangement of pin groups, including a first pin group and a second pin group;
 the first data-link group connected to the first pin group of the first socket and the second data-link group connected to the second pin group of the second socket;   the first memory module including a first data-buffer component to steer first data from the first memory module to the first pin group on the first memory module responsive to a read command; and   the second memory module including a second data-buffer component to steer second data from the second memory module to the second pin group of the second memory module responsive to the read command.   
     
     
         5 . The motherboard of  claim 4 , further comprising:
 a third memory module in the third memory-module socket; and   a fourth memory module in the fourth memory-module socket;   the first data-link group connected to the first pin group of the third socket and the second data-link group connected to the second pin group of the fourth socket;   the motherboard steering data from the third memory module to the first pin group on the third memory module responsive to the read command and steering data from the fourth memory module to the second pin group of the fourth memory module responsive to the read command.   
     
     
         6 . The motherboard of  claim 1 , each of the sockets including a similar arrangement of pin groups, including a first pin group and a second pin group, the first data-link group connected to the first pin group of the first socket and the second data-link group connected to the first pin group of the second socket. 
     
     
         7 . The motherboard of  claim 1 , each of the sockets including a similar arrangement of pin groups, including a first pin group and a second pin group, the first data-link group connected to the first pin group of the first socket and the second data-link group connected to the second pin group of the second socket. 
     
     
         8 . The motherboard of  claim 1 , further comprising:
 a third data-link group extending between the first memory-module socket and the second memory-module socket; and   a fourth data-link group extending between the third memory-module socket and the fourth memory-module socket.   
     
     
         9 . The motherboard of  claim 8 , further comprising:
 a memory module in one of the first memory-module socket and the second memory-module socket; and   a continuity module in the other of the first memory-module socket and the second memory-module socket;   the memory module coupled to the memory-controller component via a data path that includes the third data-link group connected in series with the continuity module.   
     
     
         10 . The motherboard of  claim 9 , wherein the data path includes the first data-link group connected in series with the third data-link group. 
     
     
         11 . The motherboard of  claim 8 , further comprising:
 a memory module in one of the third memory-module socket and the fourth memory-module socket; and   a continuity module in the other of the third memory-module socket and the fourth memory-module socket;   the memory module coupled to the memory-controller component via a data path that includes the fourth data-link group connected in series with the continuity module.   
     
     
         12 . The motherboard of  claim 11 , wherein the data path includes the second data-link group connected in series with the fourth data-link group. 
     
     
         13 . A memory module comprising:
 a module interface;   memory components, including a first memory component and a second memory component; and   an address-buffer component having:
 a primary address interface coupled to the module interface to receive primary memory addresses expressed as primary-address bits; 
 a primary chip-select interface coupled to the module interface to receive primary chip-select information as primary chip-select bits; 
 a first secondary chip-select interface coupled to the first memory component; and 
 a second secondary chip-select interface coupled to the second memory component; and 
 logic to direct the primary chip-select information to the first secondary chip-select interface and disable the second secondary chip-select interface responsive to a subset of the primary-address bits and a subset of the primary chip-select bits. 
   
     
     
         14 . The memory module of  claim 13 , wherein the logic disables the second secondary chip-select interface in a first mode and supports a second mode. 
     
     
         15 . The memory module of  claim 14 , the logic, in the second mode, to direct the primary chip-select information to the first secondary chip-select interface and the second secondary chip-select interface responsive to the same or a different subset of the primary-address bits and the same or a different subset of the primary chip-select bits. 
     
     
         16 . The memory module of  claim 13 , wherein the logic directs the primary chip-select information responsive to a mode signal. 
     
     
         17 . The memory module of  claim 16 , further comprising mode register to store the mode signal. 
     
     
         18 . The memory module of  claim 16 , wherein the logic derives the mode signal from at least one of the primary-address bits and the primary chip-select bits. 
     
     
         19 . The memory module of  claim 13 , further comprising a data-buffer component coupled between the module interface and the memory components, the logic coupled to the data-buffer component to alternatively connect the first memory component and the second memory component to the module interface. 
     
     
         20 . The memory module of  claim 19 , the data-buffer component including:
 a first primary data-link interface coupled to the module interface;   a second primary data-link interface coupled to the module interface;   a first secondary data-link interface coupled to the first memory component; and   a second secondary data-link interface coupled to the second memory component;   wherein the address-buffer component to issue a signal to the data-buffer component to steer data between the first primary data-link interface and one of the first and second secondary data-link interfaces, and to disable the other of the first and second secondary data-link interfaces.   
     
     
         21 . The memory module of  claim 20 , wherein the address-buffer component issues the signal to the data-buffer component to steer the data in a first mode, and wherein the address-buffer component supports a second mode to steer the data between the first primary data-link interface and the first secondary data-link interface and between the second primary data-link interface and the second secondary data-link interface. 
     
     
         22 . The memory module of  claim 21 , further comprising a mode-select terminal to receive a mode-select signal to select between the first mode and the second mode, wherein the mode-select signal initializes at least one of the address-buffer component and the data-buffer component and maintains the at least one of the address-buffer component and the data-buffer component in the mode during operation. 
     
     
         23 . The memory module of  claim 22 , further comprising a register to store the mode-select signal.