Connectable Package Extender for Semiconductor Device Package

Abstract

A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

What is claimed is: 
     
         1 . A semiconductor packaging system, comprising:
 a semiconductor device package, comprising:
 a semiconductor chip comprising two or more terminals; 
 a protective structure encapsulating and electrically insulating the semiconductor chip; 
 two or more electrical conductors extending to an outer surface of the protective structure, each one of the electrical conductors electrically connected to one of the terminals; and 
 a first surface feature on an exterior surface of the semiconductor device package; and 
   a connectable package extender, comprising:
 a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package; 
 an extension portion adjoining the second surface feature and extending away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package. 
   
     
     
         2 . The packaging system of  claim 1 , wherein the extension portion is configured to dissipate heat away from the semiconductor device package when the package extender is secured to the semiconductor device package. 
     
     
         3 . The semiconductor packaging system of  claim 1 , wherein the first surface feature is a groove in the exterior surface and wherein the second surface feature is a protrusion dimensioned to be inserted in to groove. 
     
     
         4 . The packaging system of  claim 3 , wherein the groove is a u-shaped slot comprising opposing sidewalls and a bottom surface extending between the opposing sidewalls. 
     
     
         5 . The packaging system of  claim 3 , wherein the groove is a t-shaped slot comprising:
 a narrow portion adjoining the exterior surface comprising first opposing sidewalls extending perpendicular to the exterior surface; and   a widened portion spaced apart from the exterior surface and adjoining the narrow portion, the widened portion comprising second opposing sidewalls extending perpendicular to the exterior surface and spaced further apart than the first opposing sidewalls, a top surface extending between the first and second opposing sidewalls parallel to the exterior surface, and a bottom surface extending between the second opposing sidewalls parallel to the exterior surface.   
     
     
         6 . The semiconductor packaging system of  claim 1 , wherein the first surface feature is a circular protrusion extending away from the exterior surface and wherein the second surface feature is a circular indentation dimensioned to receive the circular protrusion. 
     
     
         7 . The packaging system of  claim 1 , wherein the semiconductor device package further comprises a metal tab extending away from the protective structure, and wherein the first surface feature is formed on the metal tab. 
     
     
         8 . The packaging system of  claim 6 , wherein the metal tab extends away from a top surface of the protective structure, wherein the electrical conductors comprise leads extending away from a bottom surface of the protective structure in an opposite direction as the metal tab, and wherein the package extender is configured such that the extension portion contacts a rear surface of the protective structure between the top and bottom surfaces when the package extender is secured to the semiconductor device package. 
     
     
         9 . The packaging system of  claim 8 , wherein the package extender is formed from a thermally conductive material and comprises planar fins on the extension portion, the planar fins extending away from the rear surface of the protective structure when the package extender is secured to the semiconductor device package. 
     
     
         10 . The packaging system of  claim 8 , wherein the package extender is formed from a thermally conductive material and comprises an interior channel contacting the rear surface of the protective structure and configured to dissipate heat away from the semiconductor device package via fluid when the package extender is secured to the semiconductor device package. 
     
     
         11 . The packaging system of  claim 8 , wherein the package extender is formed from a thermally insulating material. 
     
     
         12 . The packaging system of  claim 1 , wherein the electrical conductors comprise leads arranged on a bottom surface of the protective structure and extending away from the protective structure in a direction parallel to the bottom surface, and wherein the first surface feature is arranged on one of the leads so as to space the package extender apart from the protective structure when the package extender is secured to the semiconductor device package. 
     
     
         13 . The semiconductor device packaging system of  claim 12 , wherein the semiconductor chip is a power transistor comprising source and drain terminals on top and bottom sides of the semiconductor chip, wherein the electrical conductors comprise first and second leads extending away from one another is opposite directions, wherein the source and drain terminals are electrically connected to the first and second leads, and wherein each of the first and second leads comprise the first surface feature. 
     
     
         14 . The packaging system of  claim 1 , wherein the package extender comprises an elongated member adjoining and extending away from the second surface feature in a first direction and planar fins adjoining and extending away from the elongated member in a direction substantially perpendicular to the first direction. 
     
     
         15 . The packaging system of  claim 1 , wherein the package extender comprises a plurality of elongated members extending away from the second surface feature in a first direction, the plurality of elongated members spaced apart from one other by voids extending in the first direction. 
     
     
         16 . A semiconductor device package, comprising:
 a semiconductor chip comprising two or more terminals;   a protective structure encapsulating and electrically insulating the semiconductor chip;   two or more electrical conductors, each one of the electrical conductors electrically connected to one of the terminals; and   a surface feature on an exterior surface of the package,   wherein the surface feature is configured to interlock with a surface feature of a connectable package extender so as to secure the package extender to the semiconductor device package.   
     
     
         17 . The semiconductor device package of  claim 16 , wherein the semiconductor chip is a power transistor comprising source and drain terminals on top and bottom sides of the semiconductor chip, wherein two or more electrical conductors comprise first and second leads extending away from one another in a direction parallel to the top and bottom sides, wherein the source and drain terminals are electrically connected to the first and second leads, and wherein each of the first and second leads comprise the surface feature. 
     
     
         18 . The semiconductor device package of  claim 16 , wherein the surface feature is a t-shaped slot, the t-shaped slot comprising:
 a narrow portion adjoining the exterior surface comprising first opposing sidewalls extending perpendicular to the exterior surface;   a widened portion beneath the exterior surface and adjoining the narrow portion, the widened portion comprising second opposing sidewalls extending perpendicular to the exterior surface and spaced further apart than the first opposing sidewalls, a top surface extending between the first and second opposing sidewalls parallel to the exterior surface, and a bottom surface extending between the second opposing sidewalls parallel to the exterior surface.   
     
     
         19 . A method of packaging a semiconductor chip comprising two or more terminals, the method comprising:
 providing a semiconductor device package, comprising:
 forming a protective structure encapsulating and electrically insulating the semiconductor chip; 
 forming two or more electrical conductors extending to an outer surface of the protective structure, 
 electrically connecting each of one of the electrical conductors to one of the terminals; and 
 forming a first surface feature on an exterior surface of the semiconductor device package; and 
   providing a connectable package extender, comprising:
 forming a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package, and 
 forming an extension portion adjoining the second surface feature and extending away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package. 
   
     
     
         20 . The method of  claim 19 , further comprising:
 securing the package extender to the semiconductor device package by aligning the second surface feature with the first surface feature.