US2018204814A1PendingUtilityA1

Method for preparing a semiconductor package

Assignee: NANYA TECHNOLOGY CORPPriority: Jan 19, 2017Filed: Dec 22, 2017Published: Jul 19, 2018
Est. expiryJan 19, 2037(~10.4 yrs left)· nominal 20-yr term from priority
H10W 90/723H10W 72/01257H10W 72/01223H10W 72/834H10W 72/248H10W 72/244H10W 70/63H10W 90/00H10W 74/142H10W 72/944H10W 72/926H10W 72/952H10W 72/942H10W 72/9415H10W 72/922H10W 72/29H10W 72/9413H10W 72/0198H10W 72/07236H10W 90/10H10W 72/227H10W 72/252H10W 72/241H10W 72/01255H10W 72/019H10W 74/01H10W 74/129H10W 74/10H01L 21/565H01L 2224/11849H01L 2224/1418H01L 24/13H01L 24/11H01L 2224/13026H01L 2224/16137H01L 24/14H01L 2224/1132H01L 24/16H01L 23/3114
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Claims

Abstract

The present disclosure provides a method far preparing a semiconductor package. The semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical hump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for preparing a semiconductor package, comprising:
 providing a semiconductor device having a bulk region and an edge region adjacent to the bulk region;   forming a depression in the edge region, wherein the depression exposes a side of the bulk region; and   forming a lateral bump structure in the depression, wherein the lateral bump structure is formed on the side and implements a lateral signal path of the semiconductor device.   
     
     
         2 . The method for preparing a semiconductor package of  claim 1 , comprising:
 forming a mask over an upper surface of the semiconductor device, wherein the mask has an aperture exposing a portion of the edge region; and   performing an etching process to remove a portion of the edge region exposed by the aperture to form the depression.   
     
     
         3 . The method for preparing a semiconductor package of  claim 2 , further comprising:
 forming a bumping material in the depression;   removing the mask; and   performing a thermal process to form the lateral bump structure.   
     
     
         4 . The method for preparing a semiconductor package of  claim 3 , further comprising:
 performing an etching process to increase a depth of the depression before the thermal process.   
     
     
         5 . The method for preparing a semiconductor package of  claim 3 , further comprising:
 performing a grinding process from a bottom surface of the semiconductor device to remove the edge region of the semiconductor device after the thermal process.   
     
     
         6 . The method for preparing a semiconductor package of  claim 1 ,
 forming a mask over an upper surface of the semiconductor device, wherein the mask has an opening exposing a portion of the bulk region.   
     
     
         7 . The method for preparing a semiconductor package of  claim 6 , further comprising:
 forming a bumping material in the opening;   removing the mask; and   performing a thermal process to form a vertical bump structure on the bulk region.   
     
     
         8 . The method for preparing a semiconductor package of  claim 1 , further comprising:
 forming a vertical bump structure over an upper surface of the semiconductor device and implementing a vertical signal path of the semiconductor device.   
     
     
         9 . The method for preparing a semiconductor package of  claim 8 , wherein the vertical bump structure is integrally formed with the lateral bump structure.

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