Electronic component package and electronic device including the same

Abstract

An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.

What is claimed is: 
     
         1 . An electronic component package comprising:
 a redistribution layer including a first insulating layer, a first conductive pattern disposed on a first side of the first insulating layer, and a plurality of first vias penetrating through the first insulating layer, electrically connected to the first conductive pattern and including a via V 1 ; and   an electronic component disposed on a second side of the first insulating layer opposing the first side,   wherein in a first horizontal cross-sectional plane perpendicular to a stacking direction of the redistribution layer and the electronic component: the via V 1  satisfies D 1 <D 2 , where C 1  is a virtual line along the stacking direction and passes a center of the electronic component, C 2  is the center of the via V 1 , L 1  is a virtual line connecting C 1  and C 2  parallel to a diagonal line of the electronic component, D 1  is a distance between two points in the virtual line L 1  and on an edge of the via V 1  at which the edge meets L 1 , and D 2  is the longest distance between any two points of the via V 1 ,   the plurality of first vias includes another via V 2  disposed in the virtual line L 1  on an opposite side of the via V 1  with respect to the virtual line C 1 , and having a shape substantially the same as the via V 1 ,   the longest distance D 2  is along a direction perpendicular to the diagonal line of the electronic component, and   the plurality of first vias includes at least one circular-shaped via disposed between the vias V 1  and V 2 .   
     
     
         2 . The electronic component package of  claim 1 , wherein the via V 1  and the via V 2  directly contacts with first and second electrode pads of the electronic component, respectively. 
     
     
         3 . The electronic component package of  claim 2 , wherein among the plurality of first vias, the first electrode pad directly contacts with only the via V 1 , and
 among the plurality of first vias, the second electrode pad directly contacts with only the via V 2 .   
     
     
         4 . The electronic component package of  claim 1 , wherein in the first horizontal cross-sectional plane perpendicular to the stacking direction of the redistribution layer and the electronic component, the via V 1  and the via V 2  are disposed in a regions outside a region overlapping the electronic component. 
     
     
         5 . The electronic component package of  claim 1 , wherein the vias V 1  and V 2  are respectively disposed at outmost corners of the electronic component. 
     
     
         6 . The electronic component package of  claim 1 , wherein the redistribution layer further including a second insulating layer covering the first conductive pattern, a second conductive pattern disposed on one side the second insulating layer opposing the first conductive pattern, and a plurality of second vias penetrating through the second insulating layer, electrically connecting the first conductive pattern and the second conductive pattern to each other, and including a via V 3 ,
 wherein in a second horizontal cross-sectional plane perpendicular to the stacking direction of the redistribution layer and the electronic component: the via V 3  satisfies D 3 <D 4 , where C 3  is a center of the via V 3 , L 3  is a virtual line connecting C 1  and C 3  parallel to the diagonal line of the electronic component, D 3  is a distance between two points in the virtual line L 3  and on an edge of the via V 3  at which the edge of the via V 3  meets L 3 , and D 4  is the longest distance between any two points of the via V 3 ,   the plurality of second vias includes another via V 4  disposed in the virtual line on an opposite side of the via V 3  with respect to the virtual line C 1 , and having a shape substantially the same as the via V 3 , and   the plurality of second vias includes at least one circular-shaped via disposed between the vias V 3  and V 4 .   
     
     
         7 . The electronic component package of  claim 6 , wherein the vias V 3  and V 4  are disposed at outmost corners of the electronic component opposing each other with respect to the virtual line C 1 ,
 the plurality of second vias further includes vias V 5  and V 6  each having a shape substantially the same as the via V 3 , 
 in the second horizontal cross-sectional plane perpendicular to the stacking direction of the redistribution layer and the electronic component: the via V 5  satisfies D 5 <D 6 , where C 5  is a center of the via V 5 , D 5  is a distance between two points in the virtual line L 3  and on an edge of the via V 5  at which the edge of the via V 5  meets L 3 , and D 6  is the longest distance between any two points of the via V 5 , and 
 the vias V 5  and V 6  are disposed at outmost corners of the electronic component package opposing each other with respect to the virtual line C 1 . 
 
     
     
         8 . The electronic component package of  claim 1 , further comprising:
 a passivation layer disposed below the redistribution layer and having openings exposing portions a lowermost conductive pattern of the redistribution layer; and   connection terminals disposed in the openings of the passivation layer.   
     
     
         9 . The electronic component package of  claim 8 , wherein at least one of the connection terminals is disposed in a fan-out region. 
     
     
         10 . The electronic component package of  claim 1 , further comprising an encapsulant encapsulating portions of the electronic component. 
     
     
         11 . The electronic component package of  claim 1 , further comprising a frame disposed on the redistribution layer and having a through hole;
 an encapsulant encapsulating portions of the electronic component and the frame,   wherein the electronic component is disposed in the through hole of the frame.   
     
     
         12 . The electronic component package of  claim 11 , further comprising:
 a penetration wiring penetrating through the frame; and   conductive wiring patterns disposed on both surfaces of the frame opposing each other, and connected to each other by the penetration wiring,   wherein the penetration wiring and the wiring pattern are electrically connected to the electronic component through the redistribution layer.   
     
     
         13 . The electronic component package of  claim 12 , wherein the encapsulant includes openings exposing portions of one of the conductive wiring patterns disposed on one of the surfaces of the frame. 
     
     
         14 . The electronic component package of  claim 11 , further comprising a metal layer disposed on inner surface of the through hole of the frame. 
     
     
         15 . The electronic component package of  claim 11 , wherein the frame includes a lower insulating layer and an upper insulating layer stacking on each other, a first conductive wiring pattern disposed on a lower surface of the lower insulating layer and being in contact with the redistribution layer, a second conductive wiring pattern embedded in an upper surface of the lower insulating layer and covered by the upper insulating layer, and a third conductive wiring pattern disposed on the upper insulating layer opposing the second conductive wiring patterns, and
 the first to third conductive wiring layers are electrically connected to the electronic component.   
     
     
         16 . An electronic component package comprising:
 a redistribution layer including an insulating layer, a conductive pattern disposed on a first side of the insulating layer, and a plurality of vias penetrating through the insulating layer, electrically connected to the conductive pattern and including a via V 1 ; and   an electronic component disposed on a second side of the insulating layer opposing the first side,   wherein in a horizontal cross-sectional plane perpendicular to a stacking direction of the redistribution layer and the electronic component: the via V 1  satisfies D 1 <D 2 , where C 1  is a virtual line along the stacking direction and passes a center of the electronic component, C 2  is the center of the via V 1 , L 1  is a virtual line connecting C 1  and C 2 , D 1  is a distance between two points in the virtual line L 1  and on an edge of the via V 1  at which the edge meets L 1 , and D 2  is the longest distance between any two points of the via V 1 , and   the via V 1  directly connects the conductive pattern to an electrode pad of the semiconductor chip.   
     
     
         17 . The electronic component package of  claim 16 , wherein the plurality of vias includes another via V 2  disposed at in the virtual line L 1  on an opposite side of the via V 1  with respect to the virtual line C 1 , and having a shape substantially the same as the via V 1 , and
 the plurality of vias includes at least one circular-shaped via disposed between the vias V 1  and V 2 . 
 
     
     
         18 . The electronic component package of  claim 16 , wherein among the plurality of vias, the electrode pad that is connected to the via V 1  directly contacts with only the via V 1 . 
     
     
         19 . The electronic component package of  claim 16 , wherein the vias V 1  and V 2  are respectively disposed at outmost corners of the electronic component. 
     
     
         20 . The electronic component package of  claim 16 , wherein in the horizontal cross-sectional plane perpendicular to the stacking direction of the redistribution layer and the electronic component, the distance D 1  is the shortest distance between any two points of the via V 1 .