Multi-layer barrier for cmos under array type memory device and method of making thereof

Abstract

A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.

1 . A semiconductor structure, comprising:
 a doped semiconductor material portion;   a metal-semiconductor alloy portion contacting the doped semiconductor material portion;   a device contact via structure in direct contact with the metal-semiconductor alloy portion and comprising a barrier stack and a conductive fill material portion, wherein the barrier stack includes at least two metal nitride layers and at least one silicon-nitrogen material layer, and wherein each of the at least one silicon-nitrogen material layer includes a silicon-nitrogen material in which a sum of an atomic percentage of silicon and an atomic percentage of nitrogen is at least 85%; and   at least one dielectric material layer laterally surrounding the device contact via structure.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the at least two metal nitride layers comprise silicon doped transition metal nitride layers. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein each of the at least one silicon-nitrogen material layer is located between, and contacts, a respective pair of metal nitride layers among the at least two metal nitride layers. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the barrier stack includes a horizontal portion located between the metal-semiconductor alloy portion and the conductive fill material portion, and a vertical portion that laterally surrounds the conductive fill material portion and is laterally surrounded by the at least one dielectric material layer. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein:
 each of the at least one silicon-nitrogen material layer has a thickness in a range from 0.1 nm to 2.0 nm; and   the barrier stack has a total thickness in a range from 3.0 nm to 25 nm.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein an atomic ratio of silicon atoms to nitrogen atoms in the at least one silicon-nitrogen material layer is greater than 1.0. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein:
 the at least two metal nitride layers comprise titanium, tantalum or tungsten nitride layers; and   the metal-semiconductor alloy portion comprises a transition metal silicide.   
     
     
         8 . The semiconductor structure of  claim 1 , wherein:
 the at least two metal nitride layers comprise at least three metal nitride layers;   the at least one silicon-nitrogen material layer comprises at least two silicon-nitrogen material layers; and   each of the at least two silicon-nitrogen material layers is located between, and contacts, a respective pair of metal nitride layers among the at least three metal nitride layers.   
     
     
         9 .- 11 . (canceled) 
     
     
         12 . The semiconductor structure of  claim 1 , further comprising:
 a lower level metal interconnect structure embedded within the at least one dielectric material layer and contacting the device contact via structure; and   a three-dimensional memory array overlying the lower level metal interconnect structure and comprising an alternating stack of insulating layers and word lines, and memory stack structures comprising a vertical channel and a memory film vertically extending through the alternating stack,   wherein the device contact via structure comprises a source or drain electrode of a peripheral transistor located below the three-dimensional memory array, and the doped semiconductor material portion comprises a source or drain region of the peripheral transistor.   
     
     
         13 .- 20 . (canceled) 
     
     
         21 . A semiconductor structure, comprising:
 a doped semiconductor material portion;   a metal-semiconductor alloy portion contacting the doped semiconductor material portion;   a device contact via structure in direct contact with the metal-semiconductor alloy portion and comprising a barrier stack and a conductive fill material portion, wherein the barrier stack includes at least two metal nitride layers and at least one boron-nitrogen material layer, wherein each of the at least one boron-nitrogen material layer is a continuous material layer and contains stoichiometric boron nitride or contains boron atoms and nitrogen atoms such that an atomic ratio of boron atoms to nitrogen atoms is greater than 1.0; and   at least one dielectric material layer laterally surrounding the device contact via structure.   
     
     
         22 . The semiconductor structure of  claim 21 , wherein the at least two metal nitride layers comprise boron doped transition metal nitride layers. 
     
     
         23 . The semiconductor structure of  claim 21 , wherein each of the at least one boron-nitrogen material layer is located between, and contacts, a respective pair of metal nitride layers among the at least two metal nitride layers. 
     
     
         24 . The semiconductor structure of  claim 21 , wherein the barrier stack includes a horizontal portion located between the metal-semiconductor alloy portion and the conductive fill material portion, and a vertical portion that laterally surrounds the conductive fill material portion and is laterally surrounded by the at least one dielectric material layer. 
     
     
         25 . The semiconductor structure of  claim 21 , wherein an atomic ratio of boron atoms to nitrogen atoms in the at least one boron-nitrogen material layer is greater than 1.0. 
     
     
         26 . The semiconductor structure of  claim 21 , wherein at least one of the at least one boron-nitrogen material layer is a stoichiometric boron nitride layer. 
     
     
         27 . The semiconductor structure of  claim 21 , wherein:
 the at least two metal nitride layers comprise titanium, tantalum or tungsten nitride layers; and   the metal-semiconductor alloy portion comprises a transition metal silicide.   
     
     
         28 . The semiconductor structure of  claim 21 , wherein:
 the at least two metal nitride layers comprise at least three metal nitride layers;   the at least one boron-nitrogen material layer comprises at least two boron-nitrogen material layers; and   each of the at least two boron-nitrogen material layers is located between, and contacts, a respective pair of metal nitride layers among the at least three metal nitride layers.   
     
     
         29 . The semiconductor structure of  claim 21 , wherein:
 the doped semiconductor material portion comprises boron as a primary dopant; and   the barrier stack comprises a region having a greater concentration of boron atoms than that of any region within the doped semiconductor material portion.   
     
     
         30 . The semiconductor structure of  claim 21 , further comprising:
 a lower level metal interconnect structure embedded within the at least one dielectric material layer and contacting the device contact via structure; and   a three-dimensional memory array overlying the lower level metal interconnect structure and comprising an alternating stack of insulating layers and word lines, and memory stack structures comprising a vertical channel and a memory film vertically extending through the alternating stack,   wherein the device contact via structure comprises a source or drain electrode of a peripheral transistor located below the three-dimensional memory array, and the doped semiconductor material portion comprises a source or drain region of the peripheral transistor.