US2019035796A1PendingUtilityA1

Metal layers for a three-port bit cell

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Assignee: QUALCOMM INCPriority: Feb 12, 2015Filed: Oct 3, 2018Published: Jan 31, 2019
Est. expiryFeb 12, 2035(~8.6 yrs left)· nominal 20-yr term from priority
Inventors:Niladri Narayan MojumderRitu ChabaPing-Lin LiuStanley Seungchul SongZhongze WangChoh Fei Yeap
H10P 50/00H10W 20/069H10W 20/43H10W 20/42H01L 21/76897H01L 27/11G11C 8/14H01L 27/1104H01L 23/528H01L 21/3213G11C 11/418G11C 8/16G11C 11/419H01L 23/5226H01L 27/0207H10D 89/10H10B 10/12H10B 10/00
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Claims

Abstract

An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 first means for routing current coupled to a bit cell;   third means for routing current, the third means for routing current including a write word line coupled to the bit cell; and   second means for routing current, the second means for routing current between the first means for routing current and the third means for routing current, the second means for routing current including two read word lines coupled to the bit cell.   
     
     
         2 . The apparatus of  claim 1 , wherein the bit cell is a three-port bit cell. 
     
     
         3 . The apparatus of  claim 2 , wherein the three-port bit cell includes a first read port, a second read port, and a write port. 
     
     
         4 . The apparatus of  claim 1 , wherein the first means for routing current, the second means for routing current, and the third means for routing current are patterned using a self-aligned double patterning (SADP) process. 
     
     
         5 . The apparatus of  claim 1 , wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 
     
     
         6 . The apparatus of  claim 5 , wherein the semiconductor manufacturing process comprises a 10 nm process. 
     
     
         7 . The apparatus of  claim 5 , wherein the semiconductor manufacturing process comprises a 7 nm process. 
     
     
         8 . The apparatus of  claim 1 , wherein the bit cell is included in a static random access memory (SRAM) device. 
     
     
         9 . The apparatus of  claim 1 , further comprising first means for connecting the first means for routing current to the second means for routing current. 
     
     
         10 . The apparatus of  claim 9 , further comprising second means for connecting the second means for routing current to the third means for routing current. 
     
     
         11 . The apparatus of  claim 1 , wherein the second means for routing current does not include jogs. 
     
     
         12 . The apparatus of  claim 1 , wherein a first read word line of the second means for routing current is coupled to a first read transistor of the bit cell, and wherein a second read word line of the second means for routing current is coupled to a second read transistor of the bit cell. 
     
     
         13 . The apparatus of  claim 1 , wherein the write word line of the third means for routing current is coupled to a first write transistor of the bit cell and to a second write transistor of the bit cell. 
     
     
         14 . An apparatus comprising:
 first means for routing current coupled to a bit cell;   third means for routing current, the third means for routing current including a write word line coupled to the bit cell;   second means for routing current, the second means for routing current between the first means for routing current and the third means for routing current, the second means for routing current including two read word lines coupled to the bit cell;   first means for connecting the first means for routing current to the second means for routing current; and   second means for connecting the second means for routing current to the third means for routing current.   
     
     
         15 . The apparatus of  claim 14 , wherein the bit cell is a three-port bit cell. 
     
     
         16 . The apparatus of  claim 15 , wherein the three-port bit cell includes a first read port, a second read port, and a write port. 
     
     
         17 . The apparatus of  claim 14 , wherein the first means for routing current, the second means for routing current, and the third means for routing current are patterned using a self-aligned double patterning (SADP) process. 
     
     
         18 . The apparatus of  claim 14 , wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 
     
     
         19 . The apparatus of  claim 18 , wherein the semiconductor manufacturing process comprises a 7 nm process or a 10 nm process. 
     
     
         20 . The apparatus of  claim 14 , wherein the bit cell is included in a static random access memory (SRAM) device.

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