Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Abstract

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

What is claimed is: 
     
         1 . A method for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
 transmitting, from a DVM initiator of a processor-based system of a device to the DVM network, a DVM operation;   broadcasting, by the DVM network to each of a plurality of DVM targets physically coupled to the processor-based system of the device, the same DVM operation, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the DVM network is included in a system bus of the processor-based system of the device between the DVM initiator and the plurality of DVM targets, and wherein the DVM network combines responses to the DVM operation received from the plurality of DVM targets into a single response for the DVM initiator; and   based on the DVM operation being broadcasted to the plurality of DVM target by the DVM network, performing one or more hardware functions comprising:
 turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, 
 increasing a frequency of the clock domain coupled to the DVM network or the DVM target of the plurality of DVM targets that is the target of the DVM operation, 
 terminating the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the DVM target being turned off, or 
 any combination thereof. 
   
     
     
         2 . The method of  claim 1 , wherein turning on the clock domain coupled to the DVM target of the plurality of DVM targets that is the target of the DVM operation comprises:
 asserting, by the DVM initiator, a wakeup request to the clock domain coupled to the DVM target;   blocking, by the DVM network, the DVM operation while the clock domain coupled to the DVM target is turned off;   turning on the clock domain coupled to the DVM target; and   based on the clock domain coupled to the DVM target being turned on, unblocking the DVM operation and transmitting, by the DVM network, the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation.   
     
     
         3 . The method of  claim 1 , wherein increasing the frequency of the clock domain coupled to the DVM target of the plurality of DVM targets that is the target of the DVM operation comprises:
 asserting, by the DVM initiator, a wakeup request to the clock domain coupled to the DVM target;   selecting, by a clock selector unit coupled to the DVM initiator, a non-divided version of the clock domain coupled to the DVM target; and   based on the non-divided version of the clock domain coupled to the DVM target being selected, transmitting, by the DVM network, the DVM operation to the DVM target that is the target of the DVM operation.   
     
     
         4 . The method of  claim 1 , wherein terminating the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the DVM target being turned off comprises:
 receiving, from a DVM disconnect module, a command to terminate subsequent DVM operations.   
     
     
         5 . The method of  claim 1 , wherein terminating the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the DVM target being turned off comprises:
 terminating, by the DVM network, the DVM operation; and   generating, by the DVM network, a response to the DVM operation.   
     
     
         6 . The method of  claim 1 , wherein the DVM initiator comprises a processor. 
     
     
         7 . The method of  claim 1 , wherein the DVM operation comprises a translation lookaside buffer (TLB) invalidate operation, a synchronization operation, or any combination thereof. 
     
     
         8 . The method of  claim 1 , wherein the DVM initiator is coupled to a separate clock domain and a separate power domain from a clock domain and a power domain of the DVM network. 
     
     
         9 . The method of  claim 1 , wherein the plurality of DVM targets are coupled to clock domains and power domains separate from a clock domain and a power domain of the DVM initiator and a clock domain and a power domain of the DVM network. 
     
     
         10 . The method of  claim 1 , wherein each of the plurality of DVM targets is coupled to a separate clock domain and a separate power domain from remaining ones of the plurality of DVM targets. 
     
     
         11 . The method of  claim 1 , wherein the plurality of DVM targets is coupled to a single clock domain and a power domain. 
     
     
         12 . An apparatus for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
 a DVM initiator of a processor-based system of a device;   a plurality of DVM targets physically coupled to the processor-based system of the device;   a DVM network physically coupled to the DVM initiator and the plurality of DVM targets, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the DVM network is included in a system bus of the processor-based system of the device between the DVM initiator and the plurality of DVM targets, wherein the DVM network is configured to broadcast the same DVM operation from the DVM initiator to each of the plurality of DVM targets, and wherein the DVM network combines responses to the DVM operation received from the plurality of DVM targets into a single response for the DVM initiator,   wherein, based on a DVM operation in the DVM network being broadcasted to the plurality of DVM targets:
 a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation is turned on, 
 a frequency of the clock domain coupled to the DVM network or the DVM target of the plurality of DVM targets that is the target of the DVM operation is increased, 
 the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation is terminated based on the DVM target being turned off, or 
 any combination thereof. 
   
     
     
         13 . The apparatus of  claim 12 , wherein the plurality of memory management units each comprise a translation lookaside buffer (TLB). 
     
     
         14 . The apparatus of  claim 12 , wherein the DVM initiator comprises a processor. 
     
     
         15 . The apparatus of  claim 12 , wherein the DVM operations comprise a TLB invalidate operations, synchronization operations, or any combination thereof. 
     
     
         16 . The apparatus of  claim 12 , wherein the DVM initiator is coupled to a separate clock domain and a separate power domain from a clock domain and a power domain of the DVM network. 
     
     
         17 . The apparatus of  claim 12 , wherein the plurality of DVM targets are coupled to clock domains and power domains separate from a clock domain and a power domain of the DVM initiator and a clock domain and a power domain of the DVM network. 
     
     
         18 . The apparatus of  claim 12 , wherein each of the plurality of DVM targets is coupled to a separate clock domain and a separate power domain from remaining ones of the plurality of DVM targets. 
     
     
         19 . The apparatus of  claim 12 , wherein the plurality of DVM targets is coupled to a single clock domain and a power domain. 
     
     
         20 . The apparatus of  claim 12 , wherein the DVM network reports the single response to the DVM initiator. 
     
     
         21 . The apparatus of  claim 12 , wherein based on the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation being terminated, the DVM network responds to the DVM initiator on behalf of the DVM target. 
     
     
         22 . An apparatus for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
 means for broadcasting of a processor-based system of a device communicatively coupled to a plurality of DVM targets coupled to the processor-based system of the device;   means for transmitting of the processor-based system of the device, to the means for broadcasting, a DVM operation, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the means for broadcasting is included in a system bus of the processor-based system of the device between the means for transmitting and the plurality of DVM targets, wherein the means for broadcasting is configured to broadcast, to each of the plurality of DVM targets, the same DVM operation, and wherein the means for broadcasting is configured to combine responses to the DVM operation received from the plurality of DVM targets into a single response for the means for transmitting; and   means for performing, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, one or more hardware functions comprising:
 turn on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, 
 increase a frequency of the clock domain coupled to the DVM network or the DVM target of the plurality of DVM targets that is the target of the DVM operation, 
 terminate the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the DVM target being turned off, or 
 any combination thereof. 
   
     
     
         23 . The apparatus of  claim 22 , wherein the plurality of memory management units each comprise a translation lookaside buffer (TLB). 
     
     
         24 . The apparatus of  claim 22 , wherein the DVM operations comprise a TLB invalidate operations, synchronization operations, or any combination thereof. 
     
     
         25 . The apparatus of  claim 22 , wherein the means for transmitting is coupled to a separate clock domain and a separate power domain from a clock domain and a power domain of the DVM network. 
     
     
         26 . The apparatus of  claim 22 , wherein the plurality of DVM targets are coupled to clock domains and power domains separate from a clock domain and a power domain of the means for transmitting and a clock domain and a power domain of the DVM network. 
     
     
         27 . The apparatus of  claim 22 , wherein each of the plurality of DVM targets is coupled to a separate clock domain and a separate power domain from remaining ones of the plurality of DVM targets. 
     
     
         28 . The apparatus of  claim 22 , wherein the plurality of DVM targets is coupled to a single clock domain and a power domain. 
     
     
         29 . The apparatus of  claim 22 , wherein the DVM network reports the single response to the means for transmitting. 
     
     
         30 . The apparatus of  claim 22 , wherein based on the DVM operation to the DVM target of the plurality of DVM targets that is the target of the DVM operation being terminated, the DVM network responds to the means for transmitting on behalf of the DVM target.